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公开(公告)号：US11899777B2
公开(公告)日：2024-02-13
申请号：US18179735
申请日：2023-03-07
发明人： Melvin K. Benedict , Eric L. Pope
CPC分类号： G06F21/44 , G06F13/1668 , G06F13/4282
摘要： Systems and methods are provided for a secondary authentication of a memory module. A nonce key is written to a nonce register of a register array on the memory module, the nonce register being accessible over two different interfaces. In various embodiments, the nonce key may be generated by a management system of the computing platform after performing one or more authentication processes for a memory module over a management interface. Authentication information for use in performing authentication can be stored in an identification component on the memory module. If authentication is successful, the management system can generate the nonce key and write it to the nonce register. Upon receiving a request to access an address, a memory controller can read the nonce register of the memory module at the requested address and compare the nonce key to an identifier included in the request.
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公开(公告)号：US11474706B2
公开(公告)日：2022-10-18
申请号：US14786383
申请日：2013-04-30
IPC分类号： G06F3/06 , G11C11/406 , G11C7/02 , G11C29/02 , G11C11/408 , G11C7/10 , G11C29/04
摘要： A technique includes determining, via an analog circuit, where an access rate of a memory row associated with a memory device exceeds a threshold. In various examples, upon a determination that the access rate exceeds the threshold, the technique may further comprise generating an alert to indicate possible corruption of data stored in an adjacent row to the memory row.
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公开(公告)号：US11126565B2
公开(公告)日：2021-09-21
申请号：US15193146
申请日：2016-06-27
发明人： Melvin K. Benedict
摘要： Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The memory controller includes an encryptor to control a plurality of memory access keys respectively associated with memory regions, where each memory region is allocated to a respective client, and an access manager to receive an access request from a client, the access request including a client access key to access a memory element. The access manager looks up a memory access key from a page table attribute associated with a physical address of the memory element, and determines if the access request is valid by comparing the client access key with the memory access key associated with the memory region that includes the memory element. Based on the determination and a mode of operation, the access manager provides a response to the access request.
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公开(公告)号：US10477672B2
公开(公告)日：2019-11-12
申请号：US15882649
申请日：2018-01-29
发明人： Melvin K. Benedict , Karl J. Bois
摘要： An electronic device includes a printed circuit board. The printed circuit board includes a plurality of different signaling planes and a plurality of different reference planes. A single ended via interconnects the plurality of different signaling planes. A return via interconnects the plurality of different reference planes. The electronic device includes a shared void that includes the single ended via and the return via.
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公开(公告)号：US20190025896A1
公开(公告)日：2019-01-24
申请号：US16139109
申请日：2018-09-24
发明人： Thomas Robert Bowden , Alan B. Doerr , John Franz , Melvin K. Benedict , Joseph Allen , John Norton , Binh Nguyen
IPC分类号： G06F1/20 , G06F13/42 , G06F1/18 , H01L23/40 , H01L23/367
CPC分类号： G06F1/206 , G06F1/185 , G06F1/20 , G06F13/42 , H01L23/367 , H01L23/4093 , H01L2924/0002 , H01L2924/00
摘要： A thermal management assembly in accordance with one example may include a first thermal management member that includes a first main region that is continuous, a first connection region that is discontinuous, and a first top side. The thermal management assembly may also include a second thermal management member that includes a second main region, a second connection region, and a second top side. The second main region and the second connection region are continuous. The thermal management assembly may further include a connection member to couple the first thermal management member and the second thermal management member to a memory device via the first connection region and the second connection region. The first top side and the second top side are substantially level with a top side of the memory device in a horizontal direction when the first thermal management member and the second thermal management member are coupled to the memory device.
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公开(公告)号：US20190013085A1
公开(公告)日：2019-01-10
申请号：US16066110
申请日：2016-01-26
CPC分类号： G11C29/42 , G06F11/1068 , G06F11/2215 , G11C29/02 , G11C29/52
摘要： One example includes a system. The system includes an error injection system. The error injection system includes an error injector to store a programmable control structure to define a memory error. The error injector being further used to inject the memory error into a respective one of a plurality of memory storage elements associated with a memory system at a predetermined address via an address controller and to determine if the memory error at the predetermined address associated with the respective one of the plurality of memory storage elements is corrected via error-correcting code (ECC) memory associated with the memory system.
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公开(公告)号：US09928897B2
公开(公告)日：2018-03-27
申请号：US15500070
申请日：2015-02-27
发明人： Reza M. Bacchus , Melvin K. Benedict , Stephen F. Contreras , Eric L. Pope , Chi K. Sides , Chun-Pin Huang
IPC分类号： G11C5/06 , G11C11/4074 , G11C5/10
CPC分类号： G11C11/4074 , G11C5/04 , G11C5/06 , G11C5/10 , G11C5/14 , G11C5/147 , G11C11/401
摘要： An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.
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公开(公告)号：US20170300433A1
公开(公告)日：2017-10-19
申请号：US15518195
申请日：2014-10-29
IPC分类号： G06F13/16 , G06F15/78 , H04L12/911
CPC分类号： G06F13/1668 , G06F13/1694 , G06F15/7821 , H04L47/70
摘要： A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.
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公开(公告)号：US20170124246A1
公开(公告)日：2017-05-04
申请号：US15316026
申请日：2014-07-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5045 , G06F17/5068 , G06F17/5072 , H05K3/0005 , H05K2201/09972
摘要： A method is described in which a functional region on a printed circuit board (PCB) is defined, a regional circuit design to be inserted into the functional region on the PCB is selected, and the regional circuit design is pasted into the functional region.
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公开(公告)号：US20220139791A1
公开(公告)日：2022-05-05
申请号：US17084375
申请日：2020-10-29
发明人： Melvin K. Benedict , Karl J. Bois
IPC分类号： H01L21/66 , H01L21/768
摘要： Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.
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