公开(公告)号：US10026896B2

公开(公告)日：2018-07-17

申请号：US15500050

申请日：2015-02-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Warren Jackson ,  Jianhua Yang ,  Kyung Min Kim ,  Zhiyong Li

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.

公开(公告)号：US09934849B2

公开(公告)日：2018-04-03

申请号：US15320779

申请日：2014-07-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kyung Min Kim ,  Jianhua Yang ,  Zhiyong Li

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C2013/0073 ,  G11C2213/72

Abstract: A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes a memory element to store information. The memory element is defined as an intersection between a column electrode and a row electrode of the crossbar array. Each memory cell also includes a selector to select a target memory element by relaying a first selecting voltage to a column electrode that corresponds to the target memory element and relaying a second selecting voltage to a row electrode that corresponds to the target memory element. The system also includes a controller to pass a first standing voltage to column electrodes of the crossbar array and to pass a second standing voltage to row electrodes of the crossbar array. The first standing voltage is different than the second standing voltage.

公开(公告)号：US20170206957A1

公开(公告)日：2017-07-20

申请号：US15329207

申请日：2015-01-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kyung Min Kim ,  Ning Ge ,  Jianhua Yang

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C2207/063

Abstract: A method of sensing an output signal in a crossbar array is described. In the method, a selecting voltage is applied to a target memory element of the crossbar array. Also in the method, a non-selecting voltage is applied to non-target memory elements of the crossbar array. Further in the method, a target output that is associated with the target memory element is isolated, with sensing circuitry, from a sneak output based on a time delay between arrival of the target output and the sneak output and the target output is sensed.

公开(公告)号：US20170271591A1

公开(公告)日：2017-09-21

申请号：US15500050

申请日：2015-02-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Warren Jackson ,  Jianhua Yang ,  Kyung Min Kim ,  Zhiyong Li

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/147 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/73 ,  G11C2213/77 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

Abstract: A multilayered memristor includes a semiconducting n-type layer, a semiconducting p-type layer, and a semiconducting intrinsic layer. The semiconducting n-type layer includes one or both of anion vacancies and metal cations. The semiconducting p-type layer includes one or both of metal cation vacancies and anions. The semiconducting intrinsic layer is coupled between the n-type layer and the p-type layer to form an electrical series connection through the n-type layer, the intrinsic layer, and the p-type layer.

公开(公告)号：US09934852B2

公开(公告)日：2018-04-03

申请号：US15329207

申请日：2015-01-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kyung Min Kim ,  Ning Ge ,  Jianhua Yang

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0061 ,  G11C2207/063

Abstract: A method of sensing an output signal in a crossbar array is described. In the method, a selecting voltage is applied to a target memory element of the crossbar array. Also in the method, a non-selecting voltage is applied to non-target memory elements of the crossbar array. Further in the method, a target output that is associated with the target memory element is isolated, with sensing circuitry, from a sneak output based on a time delay between arrival of the target output and the sneak output and the target output is sensed.

公开(公告)号：US20170200493A1

公开(公告)日：2017-07-13

申请号：US15320779

申请日：2014-07-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Kyung Min Kim ,  Jianhua Yang ,  Zhiyong Li

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C2013/0073 ,  G11C2213/72

Abstract: A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes a memory element to store information. The memory element is defined as an intersection between a column electrode and a row electrode of the crossbar array. Each memory cell also includes a selector to select a target memory element by relaying a first selecting voltage to a column electrode that corresponds to the target memory element and relaying a second selecting voltage to a row electrode that corresponds to the target memory element. The system also includes a controller to pass a first standing voltage to column electrodes of the crossbar array and to pass a second standing voltage to row electrodes of the crossbar array. The first standing voltage is different than the second standing voltage.