中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.017 seconds)

    APPARATUS AND METHOD FOR MULTI-MODE STORAGE
    2.
    发明申请
    APPARATUS AND METHOD FOR MULTI-MODE STORAGE 有权
    多模式存储的装置和方法

    公开(公告)号：US20150012695A1

    公开(公告)日：2015-01-08

    申请号：US13936986

    申请日：2013-07-08

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Robert J. Brooks

    IPC: G06F12/08 ,  G06F17/30

    CPC classification number: G06F17/30982 ,  G06F12/0895 ,  G11C15/00

    Abstract: According to an example, multi-mode storage may include operating a first array including a first memory and a second array including a second memory in one or more modes of operation. The first memory may be a relatively denser memory compared to the second memory and the second memory may be a relatively faster memory compared to the first memory. The modes of operation may include a first mode of operation where the first array functions as the relatively denser memory compared to the second memory and the second array functions as the relatively faster memory compared to the first memory, a second mode of operation where the second array is operated as an automatic cache of a portion of a dataset, and a third mode of operation where a cache-tag functionality used to support the second mode of operation is instead used to provide a CAM.

    Abstract translation: 根据示例，多模式存储可以包括在一个或多个操作模式中操作包括第一存储器的第一阵列和包括第二存储器的第二阵列。 与第二存储器相比，第一存储器可以是相对较密的存储器，并且与第一存储器相比，第二存储器可以是相对较快的存储器。 操作模式可以包括第一操作模式，其中与第二存储器相比，第一阵列用作相对较密的存储器，并且第二阵列用作与第一存储器相比较快的存储器，第二操作模式，其中第二操作模式 阵列作为数据集的一部分的自动缓存操作，并且替代地使用用于支持第二操作模式的缓存标签功能来提供CAM的第三操作模式。

    Apparatus and method for multi-mode storage
    3.
    发明授权
    Apparatus and method for multi-mode storage 有权
    多模式存储的装置和方法

    公开(公告)号：US09165088B2

    公开(公告)日：2015-10-20

    申请号：US13936986

    申请日：2013-07-08

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Robert J. Brooks

    IPC: G06F12/00 ,  G06F17/30 ,  G06F12/08 ,  G11C15/00

    CPC classification number: G06F17/30982 ,  G06F12/0895 ,  G11C15/00

    Abstract: According to an example, multi-mode storage may include operating a first array including a first memory and a second array including a second memory in one or more modes of operation. The first memory may be a relatively denser memory compared to the second memory and the second memory may be a relatively faster memory compared to the first memory. The modes of operation may include a first mode of operation where the first array functions as the relatively denser memory compared to the second memory and the second array functions as the relatively faster memory compared to the first memory, a second mode of operation where the second array is operated as an automatic cache of a portion of a dataset, and a third mode of operation where a cache-tag functionality used to support the second mode of operation is instead used to provide a CAM.

    Abstract translation: 根据示例，多模式存储可以包括在一个或多个操作模式中操作包括第一存储器的第一阵列和包括第二存储器的第二阵列。 与第二存储器相比，第一存储器可以是相对较密的存储器，并且与第一存储器相比，第二存储器可以是相对较快的存储器。 操作模式可以包括第一操作模式，其中与第二存储器相比，第一阵列用作相对较密的存储器，并且第二阵列用作与第一存储器相比较快的存储器，第二操作模式，其中第二操作模式 阵列作为数据集的一部分的自动缓存操作，并且替代地使用用于支持第二操作模式的缓存标签功能来提供CAM的第三操作模式。

    State-retaining logic cell
    4.
    发明授权
    State-retaining logic cell 有权

    公开(公告)号：US09742403B2

    公开(公告)日：2017-08-22

    申请号：US14781865

    申请日：2013-04-02

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Gregg B. Lesartre ,  Robert J. Brooks ,  Brent Edgar Buchanan

    IPC: H03K19/00 ,  H03K3/037 ,  H03K19/094 ,  G11C11/02 ,  G11C14/00

    CPC classification number: H03K19/0008 ,  G11C14/009 ,  H03K3/037 ,  H03K3/0375 ,  H03K19/094

    Abstract: A state-retaining logic cell may include a plurality of inverters, an output node non-volatile (NVM) storage cell, and an input node NVM storage cell. The plurality of inverters may include a feed-forward inverter and a feed-back inverter disposed in a back-to-back arrangement. The output node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an output node of the feed-forward and the feed-back inverters, and the second terminal is connected to a programming rail. The input node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an input node of the feed-forward and the feed-back inverters, and the second terminal is connected to the programming rail.

    Implementing coherency with reflective memory
    5.
    发明授权
    Implementing coherency with reflective memory 有权
    用反射记忆实现一致性

    公开(公告)号：US09575898B2

    公开(公告)日：2017-02-21

    申请号：US14763943

    申请日：2013-03-28

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Gregg B. Lesartre ,  Robert J. Brooks ,  Blaine D. Gaither

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/281

    Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

    Abstract translation: 本文描述了用于更新第一存储器件的反射存储器区域中的数据的技术。 在一个示例中，用于更新第一存储器设备的反射存储器区域中的数据的方法包括接收将数据从缓存设备刷新到第一存储器设备的指示。 该方法还包括检测与第一存储器件的反射存储器区域内的数据相对应的存储器地址，并且利用刷新操作将数据从高速缓存器件发送到第一存储器件。 此外，该方法包括确定由第一存储器设备接收的数据是修改的数据。 此外，该方法包括将修改的数据发送到第二计算系统中的第二存储器设备。

    Storage device write pulse control
    6.
    发明授权
    Storage device write pulse control 有权
    存储设备写脉冲控制

    公开(公告)号：US09490011B2

    公开(公告)日：2016-11-08

    申请号：US14903657

    申请日：2013-07-10

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Robert J. Brooks

    IPC: G11C13/00 ,  G11C8/18

    CPC classification number: G11C13/0097 ,  G11C8/18 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0092

    Abstract: According to an example, a method for storage device write pulse control may include writing a storage device to a first polarity by driving a row address line (RAL) and a column address line (CAL) to an intermediate voltage level RCA for a cycle A. The RAL may be driven to a voltage level RB for a cycle B pulse duration, and the CAL may be maintained at RCA for the cycle B pulse duration. The RAL may be driven to a voltage level RC for a cycle C pulse duration, and the CAL may be driven to a voltage level CC for the cycle C pulse duration. The RAL may be driven to RCA, and the CAL may be driven to a voltage level CD for a cycle D pulse duration. The RAL may be maintained at RCA, and the CAL may be driven to RCA.

    Abstract translation: 根据示例，用于存储设备写入脉冲控制的方法可以包括通过将行地址线（RAL）和列地址线（CAL）驱动到用于周期A的中间电压电平RCA来将存储设备写入第一极性 RAL可以被驱动到一个周期B脉冲持续时间的电压电平RB，并且对于循环B脉冲持续时间，CAL可以保持在RCA。 可以将RAL驱动到电压电平RC以获得周期C脉冲持续时间，并且CAL可以被驱动到用于周期C脉冲持续时间的电压电平CC。 RAL可以被驱动到RCA，并且CAL可以被驱动到电压电平CD以达到周期D脉冲持续时间。 RAL可以保持在RCA，CAL可以被驱动到RCA。

    MAPPING MECHANISM FOR LARGE SHARED ADDRESS SPACES
    7.
    发明申请
    MAPPING MECHANISM FOR LARGE SHARED ADDRESS SPACES 审中-公开
    大型共享地址空间的映射机制

    公开(公告)号：US20150370721A1

    公开(公告)日：2015-12-24

    申请号：US14764922

    申请日：2013-01-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Dale C. Morris ,  Russ W. Herrell ,  Gary Gostin ,  Robert J. Brooks

    IPC: G06F12/10 ,  G06F12/06

    CPC classification number: G06F12/10 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0646 ,  G06F2212/1052 ,  G06F2212/656

    Abstract: The present disclosure provides techniques for mapping large shared address spaces in a computing system. A method includes creating a physical address map for each node in a computing system. Each physical address map maps the memory of a node. Each physical address map is copied to a single address map to form a global address map that maps all memory of the computing system. The global address map is shared with all nodes in the computing system.

    Abstract translation: 本公开提供了用于在计算系统中映射大型共享地址空间的技术。 一种方法包括为计算系统中的每个节点创建物理地址图。 每个物理地址映射映射一个节点的内存。 每个物理地址映射被复制到单个地址映射以形成映射计算系统的所有存储器的全局地址映射。 全局地址映射与计算系统中的所有节点共享。

    Apparatus and method for reading a storage device with a ring oscillator and a time-to-digital circuit
    8.
    发明授权
    Apparatus and method for reading a storage device with a ring oscillator and a time-to-digital circuit 有权
    用环形振荡器和时间 - 数字电路读取存储设备的装置和方法

    公开(公告)号：US09514812B2

    公开(公告)日：2016-12-06

    申请号：US14760191

    申请日：2013-03-28

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Robert J. Brooks

    IPC: G11C7/06 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2207/066

    Abstract: According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.

    Abstract translation: 根据示例，用于存储设备读取的方法可以包括：接收指示耦合到多个存储设备的存储设备的环形振荡器的振荡周期的输入信号，以及通过以下方式测量环形振荡器的振荡周期 一个时间到数字电路。 用于存储设备读取的方法还可以包括基于测量来确定存储在存储设备中的数据的值。

    IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY
    10.
    发明申请
    IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY 有权
    用反射记忆实现相关性

    公开(公告)号：US20160026576A1

    公开(公告)日：2016-01-28

    申请号：US14763943

    申请日：2013-03-28

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Gregg B. Lesartre ,  Robert J. Brooks ,  Blaine D. Gaither

    IPC: G06F12/08

    CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/281

    Abstract: Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

    Abstract translation: 本文描述了用于更新第一存储器件的反射存储器区域中的数据的技术。 在一个示例中，用于更新第一存储器设备的反射存储器区域中的数据的方法包括接收将数据从缓存设备刷新到第一存储器设备的指示。 该方法还包括检测与第一存储器件的反射存储器区域内的数据相对应的存储器地址，并且利用刷新操作将数据从高速缓存器件发送到第一存储器件。 此外，该方法包括确定由第一存储器设备接收的数据是修改的数据。 此外，该方法包括将修改的数据发送到第二计算系统中的第二存储器设备。

Patent Agency Ranking