公开(公告)号：US20230229502A1

公开(公告)日：2023-07-20

申请号：US18186944

申请日：2023-03-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ming Chen ,  Pengxiang Yi ,  Huifeng Hu

IPC: G06F9/50

CPC classification number: G06F9/5016

Abstract: A process control method and apparatus are provided to implement intelligent control on each process in a terminal device and prevent a process important to a user from being killed while memory is released. The method includes: obtaining information, a package name, and a process name that are of a first process of a first application running on a terminal device; based on the information about the first process, determining to kill the first process; marking the package name and the process name that are of the first process; and based on marking results of a package name and a process name that are of a second process, controlling the second process.

公开(公告)号：US20230185461A1

公开(公告)日：2023-06-15

申请号：US18164262

申请日：2023-02-03

Applicant: Huawei Technologies Co., Ltd

Inventor： Hui Shen ,  Ming Chen

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0689 ,  G06F3/0659

Abstract: A redundant array of independent disks card, a command processing method, a storage apparatus and system are provided. The redundant array of independent disks card includes a control module and N front-end modules, where N is a positive integer greater than or equal to 2. An nth front-end module in the N front-end modules is configured to receive a command from an nth host module in N host modules, and send the received command to the control module. The control module is configured to receive commands from the N front-end modules and process the received commands. A storage apparatus provided with the redundant array of independent disks card can recover faulty data more quickly during data recovery. In addition, a more flexible erasure code scheme can be implemented by using the redundant array of independent disks card.

公开(公告)号：US20230124534A1

公开(公告)日：2023-04-20

申请号：US18083694

申请日：2022-12-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongchen Jin ,  Fei Luo ,  Guoyu Wang ,  Ming Chen ,  Yinzhong Tang

IPC: G11B33/04

Abstract: A storage device includes a hard disk backplane, a first cascading board, and a hard disk array. The hard disk array includes a plurality of hard disks, and is located on a first side of the hard disk backplane. The first cascading board is a field-replaceable unit FRU, and is located on a second side of the hard disk backplane.

公开(公告)号：US11550739B2

公开(公告)日：2023-01-10

申请号：US17667968

申请日：2022-02-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Can Chen ,  Xiaochu Li ,  Ming Chen

IPC: G06F13/16 ,  G06F1/26 ,  G06F3/06

Abstract: A storage system comprises a storage drive that has a physical connector A and a physical connector B for connecting to the first control device and second control device, respectively. The physical connector A and physical connector B are independent access ports. The first control device is configured to access the storage drive through the physical connector A, and the second control device is configured to access the storage drive through the physical connector B.

公开(公告)号：US20180046380A1

公开(公告)日：2018-02-15

申请号：US15797687

申请日：2017-10-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zesheng Yin ,  Ming Chen ,  Xiaofei Fu

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  H04L29/08

CPC classification number: G06F3/0607 ,  G06F3/0626 ,  G06F3/0635 ,  G06F3/0653 ,  G06F3/0685 ,  G06F12/00 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4282 ,  G06F2213/0026 ,  H04L67/24

Abstract: A peripheral component interconnect express (PCIe) storage system includes N storage devices. Each storage device includes at least one processor, a switch, and at least one storage unit. The switch includes at least two uplink ports and at least two downlink ports. The at least two uplink ports include at least one first uplink port and a second uplink port, and each processor is coupled to the at least one first uplink port. The at least two downlink ports include at least one first downlink port and a second downlink port, and the at least one storage unit is coupled to the at least one first downlink port. A second downlink port of an ith storage device is coupled to a second uplink port of an (i+1)th storage device. A second downlink port of an Nth storage device is coupled to a second uplink port of a first storage device.

公开(公告)号：US12210394B2

公开(公告)日：2025-01-28

申请号：US17866067

申请日：2022-07-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yinzhong Tang ,  Ming Chen ,  Hengchao Wang ,  Xiaochuan Li

IPC: G06F1/20 ,  G06F1/18 ,  H05K7/20

Abstract: A chassis includes a chassis body and a support, and the chassis body has a channel that passes through a first end and a second end that are of the chassis body. The support is slidably disposed in the channel. The support is provided with a first accommodation compartment, a fan compartment, and a second accommodation compartment that are successively disposed along a direction from a first end of the channel to a second end of the channel. The first accommodation compartment is capable of sliding out of the chassis body from the first end, and the second accommodation compartment is capable of sliding out of the chassis body from the second end. The fan compartment is configured to accommodate a heat dissipation fan.

公开(公告)号：US20220350377A1

公开(公告)日：2022-11-03

申请号：US17866015

申请日：2022-07-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yinzhong Tang ,  Ming Chen ,  Can Chen

IPC: G06F1/18 ,  G06F1/20 ,  H05K7/20

Abstract: A chassis includes a chassis body and an installation frame, and the chassis body has a channel that passes through a first end and a second end that are of the chassis body. The installation frame is slidably disposed in the channel of the chassis body. The installation frame has a first part facing the first end of the chassis body and a second part facing the second end of the chassis body; and the first part is capable of sliding out from the first end of the chassis body, and the second part is capable of sliding out from the second end of the chassis body.

公开(公告)号：US11082135B2

公开(公告)日：2021-08-03

申请号：US16230891

申请日：2018-12-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Michael Zarubinsky ,  Doron Cohen ,  Qingsong Xue ,  Dori Gidron ,  Ling Liu ,  Changsong Xie ,  Liangchuan Li ,  Ming Chen

IPC: H04B10/69 ,  H04L25/03 ,  H04B7/0413 ,  H04L27/26

Abstract: The present disclosure relates to an apparatus and method of processing a digital signal, wherein an input signal is transformed into the frequency domain by applying a fast Fourier transformation (FFT) processing to obtain a transformed input signal. Positive and negative frequency components of the transformed input signal are separated and respective ones of the separated positive and negative frequency components are separately processed by respective digital filtering to obtain filtered frequency components. The filtered frequency components are combined in the frequency domain using a down-sampling operation for down-sampling the filtered frequency components from an input number of samples per symbol to a different output number of samples per symbol, and the combined output components are converted into the time domain by applying an IFFT processing.

公开(公告)号：US10437473B2

公开(公告)日：2019-10-08

申请号：US15797687

申请日：2017-10-30

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zesheng Yin ,  Ming Chen ,  Xiaofei Fu

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40 ,  H04L29/08 ,  G06F12/00

Abstract: A peripheral component interconnect express (PCIe) storage system includes N storage devices. Each storage device includes at least one processor, a switch, and at least one storage unit. The switch includes at least two uplink ports and at least two downlink ports. The at least two uplink ports include at least one first uplink port and a second uplink port, and each processor is coupled to the at least one first uplink port. The at least two downlink ports include at least one first downlink port and a second downlink port, and the at least one storage unit is coupled to the at least one first downlink port. A second downlink port of an ith storage device is coupled to a second uplink port of an (i+1)th storage device. A second downlink port of an Nth storage device is coupled to a second uplink port of a first storage device.

公开(公告)号：US20190123834A1

公开(公告)日：2019-04-25

申请号：US16230891

申请日：2018-12-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Michael Zarubinsky ,  Doron Cohen ,  Qingsong Xue ,  Dori Gidron ,  Ling Liu ,  Changsong Xie ,  Liangchuan Li ,  Ming Chen

IPC: H04B10/69 ,  H04L25/03 ,  H04B7/0413 ,  H04L27/26

Abstract: The present disclosure relates to an apparatus and method of processing a digital signal, wherein an input signal is transformed into the frequency domain by applying a fast Fourier transformation (FFT) processing to obtain a transformed input signal. Positive and negative frequency components of the transformed input signal are separated and respective ones of the separated positive and negative frequency components are separately processed by respective digital filtering to obtain filtered frequency components. The filtered frequency components are combined in the frequency domain using a down-sampling operation for down-sampling the filtered frequency components from an input number of samples per symbol to a different output number of samples per symbol, and the combined output components are converted into the time domain by applying an IFFT processing.