公开(公告)号：US20110080792A1

公开(公告)日：2011-04-07

申请号：US12575137

申请日：2009-10-07

申请人： Hagop Nazarian ,  Richard Fastow

发明人： Hagop Nazarian ,  Richard Fastow

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

摘要： Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

摘要翻译： 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

公开(公告)号：US08520437B2

公开(公告)日：2013-08-27

申请号：US13600527

申请日：2012-08-31

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20120327717A1

公开(公告)日：2012-12-27

申请号：US13600527

申请日：2012-08-31

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C16/26 ,  H01L27/088 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20110317466A1

公开(公告)日：2011-12-29

申请号：US12824352

申请日：2010-06-28

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C5/06 ,  H01L21/82

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US08681558B2

公开(公告)日：2014-03-25

申请号：US12575137

申请日：2009-10-07

申请人： Hagop Nazarian ,  Richard Fastow

发明人： Hagop Nazarian ,  Richard Fastow

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

摘要： Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

摘要翻译： 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

公开(公告)号：US08279674B2

公开(公告)日：2012-10-02

申请号：US12824352

申请日：2010-06-28

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US08134853B2

公开(公告)日：2012-03-13

申请号：US12642162

申请日：2009-12-18

申请人： Richard Fastow ,  Hagop Nazarian

发明人： Richard Fastow ,  Hagop Nazarian

IPC分类号： G11C5/06 ,  G11C7/06 ,  H01L21/336

CPC分类号： G11C16/24 ,  G11C16/26

摘要： Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices.

摘要翻译： 本文公开了提供实现快速编程，擦除和读取时间的串行阵列半导体架构。 作为示例，存储器架构可以包括耦合到阵列的一端处的电子存储器件的金属位线的半导体串联阵列，以及位于阵列的相对端的传输晶体管的栅极。 此外，第二金属位线耦合到传输晶体管的漏极。 测量由通过晶体管的栅极电位调制的第二金属位线处的电流或电压的感测电路可以确定串联阵列的晶体管的状态。 由于传输晶体管的低电容，串行阵列可以快速地对传输晶体管的栅极进行充电或放电，导致与常规串行半导体阵列器件相比显着减少的读取时间。

公开(公告)号：US20110149630A1

公开(公告)日：2011-06-23

申请号：US12642162

申请日：2009-12-18

申请人： Richard Fastow ,  Hagop Nazarian

发明人： Richard Fastow ,  Hagop Nazarian

IPC分类号： G11C5/06 ,  G11C7/06 ,  H01L21/336

CPC分类号： G11C16/24 ,  G11C16/26

摘要： Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices.

摘要翻译： 本文公开了提供实现快速编程，擦除和读取时间的串行阵列半导体架构。 作为示例，存储器架构可以包括耦合到阵列的一端处的电子存储器件的金属位线的半导体串联阵列，以及位于阵列的相对端的传输晶体管的栅极。 此外，第二金属位线耦合到传输晶体管的漏极。 测量由通过晶体管的栅极电位调制的第二金属位线处的电流或电压的感测电路可以确定串联阵列的晶体管的状态。 由于传输晶体管的低电容，串行阵列可以快速地对传输晶体管的栅极进行充电或放电，导致与常规串行半导体阵列器件相比显着减少的读取时间。

公开(公告)号：US06737703B1

公开(公告)日：2004-05-18

申请号：US10095512

申请日：2002-03-12

申请人： Richard Fastow ,  Sameer Haddad ,  Yu Sun

发明人： Richard Fastow ,  Sameer Haddad ,  Yu Sun

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： In a memory device, a substrate has a plurality of source/drain regions in the substrate. Between the source/drain regions are trenches filled with oxide. Individual bit lines in the form of conductive regions are provided in the substrate, each bit line being under and running along the oxide in a trench. Each bit line connects to source/drain regions by means of connecting conductive regions extending from that bit line to source/drain regions.

摘要翻译： 在存储器件中，衬底在衬底中具有多个源极/漏极区域。 在源极/漏极区之间是填充有氧化物的沟槽。 导电区域形式的单个位线设置在衬底中，每个位线沿着沟槽中的氧化物在下面并且沿着其延伸。 每个位线通过将从该位线延伸的导电区域连接到源极/漏极区域而连接到源极/漏极区域。

公开(公告)号：US06541338B2

公开(公告)日：2003-04-01

申请号：US09917182

申请日：2001-07-30

申请人： Zhigang Wang ,  Yue-Song He ,  Richard Fastow

发明人： Zhigang Wang ,  Yue-Song He ,  Richard Fastow

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.

摘要翻译： 一种形成具有低能量源注入和高能量VSS连接注入的闪存EEPROM器件的方法，使得本征源缺陷密度降低并且VSs电阻低。 源区域注入低能量，低剂量掺杂剂离子，VSS区域注入高能量，高剂量掺杂剂离子。