公开(公告)号：US20120327717A1

公开(公告)日：2012-12-27

申请号：US13600527

申请日：2012-08-31

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C16/26 ,  H01L27/088 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20110317466A1

公开(公告)日：2011-12-29

申请号：US12824352

申请日：2010-06-28

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C5/06 ,  H01L21/82

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US08520437B2

公开(公告)日：2013-08-27

申请号：US13600527

申请日：2012-08-31

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US08279674B2

公开(公告)日：2012-10-02

申请号：US12824352

申请日：2010-06-28

申请人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

发明人： Richard Fastow ,  Hagop Nazarian ,  Lei Xue

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06

CPC分类号： G11C16/0483 ,  G11C5/063 ,  H01L27/0207 ,  H01L27/11529 ,  H01L27/11573

摘要： Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.

摘要翻译： 本文描述了提供与常规串行阵列存储器相比实现高读取速度的串行阵列存储器晶体管架构。 作为示例，串行阵列存储器可以连接到并且可以驱动小电容通过晶体管的栅极电压，以便于感测串行阵列的存储器晶体管。 传输晶体管调制相邻金属位线处的电流或电压，其可用于感测存储器晶体管的编程或擦除状态。 由于传输晶体管的小电容，串行阵列的读延迟可以显着低于常规串行阵列存储器（例如，NAND存储器）。 此外，描述了用于形成包括离散传输晶体管的串行阵列存储器的放大器区域的各种机制，以促进串行阵列存储晶体管架构的有效制造。

公开(公告)号：US20110080792A1

公开(公告)日：2011-04-07

申请号：US12575137

申请日：2009-10-07

申请人： Hagop Nazarian ,  Richard Fastow

发明人： Hagop Nazarian ,  Richard Fastow

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

摘要： Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

摘要翻译： 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

公开(公告)号：US08681558B2

公开(公告)日：2014-03-25

申请号：US12575137

申请日：2009-10-07

申请人： Hagop Nazarian ,  Richard Fastow

发明人： Hagop Nazarian ,  Richard Fastow

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0491 ,  G11C5/06 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/10

摘要： Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories.

摘要翻译： 本文描述了提供非易失性存储器架构和存储器处理技术的新组合。 作为示例，公开了与基于通道的处理技术相结合的并行位线半导体架构。 基于通道的处理技术提供快速的程序/擦除时间，相对较高的密度和良好的可扩展性。 此外，并行位线架构可实现与基于漏极的隧道工艺相当的非常快的读取时间，实现了比常规非易失性存储器更好的快速程序，擦除和读取时间的组合。

公开(公告)号：US08134853B2

公开(公告)日：2012-03-13

申请号：US12642162

申请日：2009-12-18

申请人： Richard Fastow ,  Hagop Nazarian

发明人： Richard Fastow ,  Hagop Nazarian

IPC分类号： G11C5/06 ,  G11C7/06 ,  H01L21/336

CPC分类号： G11C16/24 ,  G11C16/26

摘要： Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices.

摘要翻译： 本文公开了提供实现快速编程，擦除和读取时间的串行阵列半导体架构。 作为示例，存储器架构可以包括耦合到阵列的一端处的电子存储器件的金属位线的半导体串联阵列，以及位于阵列的相对端的传输晶体管的栅极。 此外，第二金属位线耦合到传输晶体管的漏极。 测量由通过晶体管的栅极电位调制的第二金属位线处的电流或电压的感测电路可以确定串联阵列的晶体管的状态。 由于传输晶体管的低电容，串行阵列可以快速地对传输晶体管的栅极进行充电或放电，导致与常规串行半导体阵列器件相比显着减少的读取时间。

公开(公告)号：US20110149630A1

公开(公告)日：2011-06-23

申请号：US12642162

申请日：2009-12-18

申请人： Richard Fastow ,  Hagop Nazarian

发明人： Richard Fastow ,  Hagop Nazarian

IPC分类号： G11C5/06 ,  G11C7/06 ,  H01L21/336

CPC分类号： G11C16/24 ,  G11C16/26

摘要： Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices.

摘要翻译： 本文公开了提供实现快速编程，擦除和读取时间的串行阵列半导体架构。 作为示例，存储器架构可以包括耦合到阵列的一端处的电子存储器件的金属位线的半导体串联阵列，以及位于阵列的相对端的传输晶体管的栅极。 此外，第二金属位线耦合到传输晶体管的漏极。 测量由通过晶体管的栅极电位调制的第二金属位线处的电流或电压的感测电路可以确定串联阵列的晶体管的状态。 由于传输晶体管的低电容，串行阵列可以快速地对传输晶体管的栅极进行充电或放电，导致与常规串行半导体阵列器件相比显着减少的读取时间。

公开(公告)号：US08796658B1

公开(公告)日：2014-08-05

申请号：US13466008

申请日：2012-05-07

申请人： Hagop Nazarian ,  Sung Hyun Jo

发明人： Hagop Nazarian ,  Sung Hyun Jo

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L45/1641 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/148 ,  H01L45/165 ,  H01L45/1675

摘要： A resistive memory device includes a first metallic layer comprising a source of positive metallic ions, a switching media having an upper surface and a lower surface, wherein the upper surface is adjacent to the first metallic layer, wherein the switching media comprises conductive filaments comprising positive metallic ions from the source of positive metallic ions formed from the upper surface towards the lower surface, a semiconductor substrate, a second metallic layer disposed above the semiconductor substrate, a non-metallic conductive layer disposed above the second metallic layer, and an interface region between the non-metallic conductive layer and the switching media having a negative ionic charge.

摘要翻译： 电阻式存储器件包括包含正金属离子源的第一金属层，具有上表面和下表面的开关介质，其中上表面与第一金属层相邻，其中开关介质包括包含正极的导电细丝 从上表面朝向下表面形成的正金属离子源的金属离子，半导体衬底，设置在半导体衬底上方的第二金属层，设置在第二金属层上方的非金属导电层，以及界面区域 在非金属导电层和具有负离子电荷的开关介质之间。

公开(公告)号：US08723154B2

公开(公告)日：2014-05-13

申请号：US12894057

申请日：2010-09-29

申请人： Sung Hyun Jo ,  Hagop Nazarian

发明人： Sung Hyun Jo ,  Hagop Nazarian

IPC分类号： H01L29/12 ,  H01L29/8605 ,  H01L27/105 ,  H01L21/8239

CPC分类号： H01L45/1233 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1675 ,  H01L45/1683

摘要： An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device.

摘要翻译： 集成电路器件。 集成电路器件包括具有表面区域的半导体衬底。 栅极电介质层覆盖在衬底的表面区域上。 该器件包括具有p +有源区的MOS器件。 p +有源区形成用于电阻式开关器件的第一电极。 电阻开关器件包括覆盖p +有源区的非晶硅开关材料和覆盖在第一金属导体结构上的金属电极。 金属电极包括金属材料，当对金属电极施加正偏压时，在非晶硅开关材料中形成金属区域。 MOS器件为集成电路器件提供选择晶体管。