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公开(公告)号：US5708625A
公开(公告)日：1998-01-13
申请号：US415512
申请日：1995-04-03
申请人： Hajime Sato , Takaaki Furuyama
发明人： Hajime Sato , Takaaki Furuyama
IPC分类号： G01R19/165 , G11C8/18 , G11C11/408 , H03K5/1252 , G11C7/00
CPC分类号： G11C8/18
摘要： A voltage level detector insusceptible to noise is disclosed. The voltage level detector includes a detector section, an output circuit section coupled to the detector section, and a delay circuit section provided between the detector section and the output circuit section. The detector section receives a target signal, and determines if the voltage level of the target signal lies within a predetermined voltage zone. The output circuit section outputs a detection signal when the target signal is found to be in the predetermined zone by the detector section. When the detector section detects that the target signal has come off the predetermined voltage zone, the delay circuit section delays the vanishing of the detection signal output from the output circuit section by a given delay time.
摘要翻译： 公开了一种不易受噪声影响的电压电平检测器。 电压电平检测器包括检测器部分，耦合到检测器部分的输出电路部分和设置在检测器部分和输出电路部分之间的延迟电路部分。 检测器部分接收目标信号，并且确定目标信号的电压电平是否位于预定电压区域内。 当检测器部分发现目标信号处于预定区域时，输出电路部分输出检测信号。 当检测器部分检测到目标信号已经脱离预定电压区域时，延迟电路部分将从输出电路部分输出的检测信号消失延迟给定的延迟时间。
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公开(公告)号：US08031537B2
公开(公告)日：2011-10-04
申请号：US12987466
申请日：2011-01-10
申请人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
发明人： Makoto Niimi , Kenji Nagai , Takaaki Furuyama
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F1/10 , G11C7/109
摘要： In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
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公开(公告)号：US20060002196A1
公开(公告)日：2006-01-05
申请号：US11173735
申请日：2005-07-01
申请人： Takaaki Furuyama , Satoru Kawamoto
发明人： Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C7/10
摘要： A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.
摘要翻译： 存储器系统（1A）包括存储器部分（2A）和存储器控制部分（3A）。 存储部分（2A）包括测试电路（4A），数据寄存器（5A），数据输出部分（6A）和存储器核心部分（9A）。 数据DI保存在数据电阻（5A）中。 测试电路（4A）响应于测试信号TEST将写入禁止信号WINH输出到存储器芯部分（9A）。 识别写入指令被输入到存储部分（2A）和选择信号S的写指令识别信号WR被反转，并且作为响应，数据寄存器（5A）的保留数据DR被输出作为输出数据DO 从数据输出部分（6A）。 因此，可以测试写命令CMD和数据DI的生成，传播或识别操作是否正常，而不执行将数据写入存储器部分的存储单元的操作。
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公开(公告)号：US20050185483A1
公开(公告)日：2005-08-25
申请号：US11061365
申请日：2005-02-18
申请人： Akira Sugiura , Takaaki Furuyama
发明人： Akira Sugiura , Takaaki Furuyama
CPC分类号： G11C29/82 , G11C29/70 , G11C29/808
摘要： A semiconductor memory device includes a memory block having memory cells connected to global bit lines and global word lines are arranged in matrix constitutes a memory block column sharing global bit lines, the memory block column being developed in global word line wiring direction, wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit, and redundant block(s), which is/are arranged sharing global bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit and number of redundant block(s) is/are smaller than that of memory block column(s) included in the to-be-remedied unit. A minimum number of redundant memory blocks necessary for defectiveness remedy can be provided thereby enhancing the yield with optimization of the manufacturing and circuits. Redundancy remedy efficiency can also be improved while minimizing increased chip die size of the semiconductor memory device.
摘要翻译： 半导体存储器件包括具有连接到全局位线的存储器单元的存储器块，并且矩阵排列的全局字线构成共享全局位线的存储器块列，所述存储器块列在全局字线布线方向上显影，其中至少 彼此相邻的两个存储器块列构成待修复的单元，并且被配置为与存储器块列共享全局位线的冗余块，每一个被提供在每个到 补救单元和冗余块的数量小于待修复单元中包含的存储块列的数量。 可以提供缺陷补救所需的最少数量的冗余存储块，从而通过优化制造和电路来提高产量。 还可以提高冗余补救效率，同时最小化半导体存储器件的芯片尺寸增加。
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5.发明申请公开(公告)号：US20050185482A1
公开(公告)日：2005-08-25
申请号：US11061307
申请日：2005-02-18
CPC分类号： G11C29/81
摘要： An address identifying memory block is match-compared with address information stored in a to-be-remedied block memory section in a block redundancy judge section. A redundant block select signal is outputted from the block redundancy judge section by judgment of address match. A memory block column select section selects a memory block column having a redundant memory block irrespective of an address signal as the redundant block select signal is activated if block redundancy is activated to output a memory block column select signal. A column redundancy memory section selects address information of column redundancy relating a redundant memory block arranged in a memory block column in accordance with the memory block column select signal.
摘要翻译： 地址识别存储器块与块冗余判断部分中存储在待修复块存储器部分中的地址信息进行匹配比较。 通过地址匹配的判断从块冗余判断部分输出冗余块选择信号。 如果块冗余被激活以输出存储块列选择信号，则存储块列选择部分选择具有冗余存储块而不管地址信号的存储块列，因为冗余块选择信号被激活。 列冗余存储器部分根据存储器块列选择信号选择与排列在存储器块列中的冗余存储器块有关的列冗余的地址信息。
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6.发明授权Method and apparatus for address allotting and verification in a semiconductor device 有权用于半导体器件中的地址分配和验证的方法和装置公开(公告)号：US07433219B2
公开(公告)日：2008-10-07
申请号：US11341029
申请日：2006-01-27
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译： 半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。 利用这种结构，将不同的行地址分配给操作设置信息的各个功能。 因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。
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公开(公告)号：US07281180B2
公开(公告)日：2007-10-09
申请号：US11173735
申请日：2005-07-01
申请人： Takaaki Furuyama , Satoru Kawamoto
发明人： Takaaki Furuyama , Satoru Kawamoto
摘要： A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.
摘要翻译： 存储器系统（1A）包括存储器部分（2A）和存储器控制部分（3A）。 存储部分（2A）包括测试电路（4A），数据寄存器（5A），数据输出部分（6A）和存储器核心部分（9A）。 数据DI保存在数据电阻（5A）中。 测试电路（4A）响应于测试信号TEST将写入禁止信号WINH输出到存储器芯部分（9A）。 识别写入指令被输入到存储部分（2A）和选择信号S的写指令识别信号WR被反转，并且作为响应，数据寄存器（5A）的保留数据DR被输出作为输出数据DO 从数据输出部分（6A）。 因此，可以测试写命令CMD和数据DI的生成，传播或识别操作是否正常，而不执行将数据写入存储器部分的存储单元的操作。
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公开(公告)号：US20060227629A1
公开(公告)日：2006-10-12
申请号：US11378444
申请日：2006-03-16
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译： 访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测列地址CADD，突发地址和更新字之后读出存储的数据 行新选择存储单元MC。 在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。 在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在 分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。 操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。 为每个访问操作选择合适的操作条件。
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公开(公告)号：US07061816B2
公开(公告)日：2006-06-13
申请号：US11061365
申请日：2005-02-18
申请人： Akira Sugiura , Takaaki Furuyama
发明人： Akira Sugiura , Takaaki Furuyama
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/70 , G11C29/808
摘要： A semiconductor memory device includes a memory block having memory cells connected to global bit lines and global word lines are arranged in matrix constitutes a memory block column sharing global bit lines, the memory block column being developed in global word line wiring direction, wherein at least two of memory block columns adjoining each other constitute a to-be-remedied unit, and redundant block(s), which is/are arranged sharing global bit lines with the memory block column(s), which is/are provided in each to-be-remedied unit and number of redundant block(s) is/are smaller than that of memory block column(s) included in the to-be-remedied unit. A minimum number of redundant memory blocks necessary for defectiveness remedy can be provided thereby enhancing the yield with optimization of the manufacturing and circuits. Redundancy remedy efficiency can also be improved while minimizing increased chip die size of the semiconductor memory device.
摘要翻译： 半导体存储器件包括具有连接到全局位线的存储器单元的存储器块，并且矩阵排列的全局字线构成共享全局位线的存储器块列，所述存储器块列在全局字线布线方向上显影，其中至少 彼此相邻的两个存储器块列构成待修复的单元，并且被配置为与存储器块列共享全局位线的冗余块，每一个被提供在每个到 补救单元和冗余块的数量小于待修复单元中包含的存储块列的数量。 可以提供缺陷补救所需的最少数量的冗余存储块，从而通过优化制造和电路来提高产量。 还可以提高冗余补救效率，同时最小化半导体存储器件的芯片尺寸增加。
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公开(公告)号：US06643758B2
公开(公告)日：2003-11-04
申请号：US09984357
申请日：2001-10-30
申请人： Takaaki Furuyama , Mitsuhiro Nagao
发明人： Takaaki Furuyama , Mitsuhiro Nagao
IPC分类号： G06F1200
CPC分类号： G11C16/08 , G06F12/0653 , G06F2212/2022 , G11C16/20
摘要： According to one aspect of the present invention, the flash memory comprises a memory region divided into a plurality of real banks, wherein from among the plurality of products which consists of a plurality of combinations of virtual banks having at least one real bank; and a combination of the top boot in which the most significant address is allocated to the boot bank having the boot sector and the bottom boot in which the least significant address is allocated to the boot bank, product information data are set in a product information record section, whereby any product can be configured.
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