公开(公告)号：US5614751A

公开(公告)日：1997-03-25

申请号：US632052

申请日：1996-04-15

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L27/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7397 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813

摘要： A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

摘要翻译： 用于沟槽MOSFET或其他半导体器件的端接结构（沿着晶体管周边或管芯边缘）防止不期望的表面沟道现象，而不需要任何额外的掩蔽步骤来形成通道停止。 这种结构特别适用于P沟道MOSFET。 在现有技术中，掩模限定掺杂通道阻挡。 而是在有源区域掩蔽处理之后进行P型离子的覆盖离子注入。 因此，在由场氧化物制造期间，该掺杂沟道停止终止实际上被掩蔽。 在另一个版本中，通道停止端接是在MOSFET的端接区域中形成的另外的沟槽。 沟槽通常衬有氧化物，并填充有延伸到模具边缘的导电多晶硅场板。 在另一个版本中，掺杂和沟槽通道停止组合使用。 通过在模具表面上提供覆盖它们的场板来增强通道停止。

公开(公告)号：US5429964A

公开(公告)日：1995-07-04

申请号：US180265

申请日：1994-01-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US5341011A

公开(公告)日：1994-08-23

申请号：US31798

申请日：1993-03-15

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Hamza Yilmaz

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Hamza Yilmaz

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1095 ,  H01L29/7813 ,  H01L29/0847 ,  Y10S148/103 ,  Y10S438/965

摘要： A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

摘要翻译： 具有沟槽栅极的DMOS晶体管形成在衬底中，使得晶体管的P体区域可以形成得更重或更深，同时保持“短”通道。 这是通过在形成沟槽之前在P体区域内形成N +型源区的一部分，然后在形成在P体区域的一部分上形成的N +源区的相对较浅的延伸部进行第二注入和扩散来实现的 。 P体区域的增加的深度或掺杂浓度有利地降低P体区域的电阻，而短通道降低晶体管的导通电阻以提高性能。

公开(公告)号：US5474943A

公开(公告)日：1995-12-12

申请号：US289358

申请日：1994-08-11

申请人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Hamza Yilmaz

发明人： Fwu-Iuan Hshieh ,  Mike F. Chang ,  Hamza Yilmaz

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/1095 ,  H01L29/7813 ,  H01L29/0847 ,  Y10S148/103 ,  Y10S438/965

摘要： A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

摘要翻译： 具有沟槽栅极的DMOS晶体管形成在衬底中，使得晶体管的P体区域可以形成得更重或更深，同时保持“短”通道。 这是通过在形成沟槽之前在P体区域内形成N +型源区的一部分，然后在形成在P体区域的一部分上形成的N +源区的相对较浅的延伸部进行第二注入和扩散来实现的 。 P体区域的增加的深度或掺杂浓度有利地降低P体区域的电阻，而短通道降低晶体管的导通电阻以提高性能。

公开(公告)号：US5304831A

公开(公告)日：1994-04-19

申请号：US881589

申请日：1992-05-12

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh ,  Mike Chang ,  Jun W. Chen ,  King Owyang ,  Dorman C. Pitzer ,  Jan Van Der Linde

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/322 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L27/01

CPC分类号： H01L21/28167 ,  H01L21/02129 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/3221 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811

摘要： A submicron channel length is achieved in cells having sharp corners, such as square cells, by blunting the corners of the cells. In this way, the three dimensional diffusion effect is minimized, and punch through is avoided. Techniques are discussed for minimizing defects in the shallow junctions used for forming the short channel, including the use of a thin dry oxide rather than a thicker steam thermal over the body contact area, a field shaping p+ diffusion to enhance breakdown voltage, and TCA gathering. Gate-source leakage is reduced with extrinsic gathering on the poly backside, and intrinsic gathering due to the choice of starting material. Five masking step and six masking step processes are also disclosed for manufacturing a power MOSFET structure. This power MOSFET structure has an active region with a plurality of active cells as well as a termination region with a field ring or a row of inactive cells and a polysilicon field plate.

摘要翻译： 通过钝化细胞的角落，在具有尖角的细胞（例如方形细胞）中实现亚微米通道长度。 以这种方式，三维扩散效果被最小化，避免了穿孔。 讨论了用于最小化用于形成短通道的浅结中的缺陷的技术，包括在身体接触区域上使用薄的干燥氧化物而不是较厚的蒸汽热，场成形p +扩散以增强击穿电压，以及TCA聚集 。 栅极源泄漏减少，聚合背面外部聚集，由于起始材料的选择而导致内部聚集。 还公开了五个掩模步骤和六个掩模步骤工艺，用于制造功率MOSFET结构。 该功率MOSFET结构具有具有多个有源单元的有源区以及具有场环或一行非活性单元和多晶硅场板的终端区。

公开(公告)号：US5770503A

公开(公告)日：1998-06-23

申请号：US895004

申请日：1997-07-17

申请人： Fwu-Iuan Hshieh ,  Hamza Yilmaz ,  Mike Chang

发明人： Fwu-Iuan Hshieh ,  Hamza Yilmaz ,  Mike Chang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7802

摘要： A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.

摘要翻译： 公开了一种低阈值电压功率DMOS晶体管结构，其具有在相对轻掺杂的外延硅的浅层中形成的轻掺杂沟道区。 由于外延掺杂浓度不均匀，浅外延层的掺杂使阈值电压的变化和穿通敏感性的局部变化最小化。 将相对重掺杂的外延层设置在浅掺杂的浅层外延层的下面，以减少漏极 - 源极电阻RDS。 因为相对重掺杂的外延层位于沟道区下方，而不在最易受体区穿透的结构区域内，所以提供相对高掺杂的外延层不会引起阈值电压的变化，并且不会引起变化 出现穿过身体区域穿孔的反向偏置电压。

公开(公告)号：US5597765A

公开(公告)日：1997-01-28

申请号：US423588

申请日：1995-04-17

申请人： Hamza Yilmaz ,  Fwu-Iuan Hshieh

发明人： Hamza Yilmaz ,  Fwu-Iuan Hshieh

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L27/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L29/7397 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813

摘要： A termination structure (located along a transistor perimeter or a die edge) for a trenched MOSFET or other semiconductor device prevents the undesirable surface channelling phenomena without the need for any additional masking steps to form a channel stop. This structure is especially applicable to P-channel MOSFETs. In the prior art a mask defines a doped channel stop. Instead here, a blanket ion implantation of P-type ions is performed after the active area masking process. Thus this doped channel stop termination is in effect masked during fabrication by the field oxide. In another version the channel stop termination is an additional trench formed in the termination region of the MOSFET. The trench is conventionally lined with oxide and filled with a conductive polysilicon field plate which extends to the edge of the die. In another version, the doped and trenched channel stops are used in combination. The channel stops are enhanced by provision of field plates overlying them on the die surface.

摘要翻译： 用于沟槽MOSFET或其他半导体器件的端接结构（沿着晶体管周边或管芯边缘）防止不期望的表面沟道现象，而不需要任何额外的掩蔽步骤来形成通道停止。 这种结构特别适用于P沟道MOSFET。 在现有技术中，掩模限定掺杂通道阻挡。 而是在有源区域掩蔽处理之后进行P型离子的覆盖离子注入。 因此，在由场氧化物制造期间，该掺杂沟道停止终止实际上被掩蔽。 在另一个版本中，通道停止端接是在MOSFET的端接区域中形成的另外的沟槽。 沟槽通常衬有氧化物，并填充有延伸到模具边缘的导电多晶硅场板。 在另一个版本中，掺杂和沟槽通道停止组合使用。 通过在模具表面上提供覆盖它们的场板来增强通道停止。

公开(公告)号：US5479037A

公开(公告)日：1995-12-26

申请号：US131114

申请日：1993-10-01

申请人： Fwu-Iuan Hshieh ,  Hamza Yilmaz ,  Mike Chang

发明人： Fwu-Iuan Hshieh ,  Hamza Yilmaz ,  Mike Chang

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7802

摘要： A low threshold voltage power DMOS transistor structure is disclosed having a lightly doped channel region formed in a shallow layer of relatively lightly doped epitaxial silicon. The light doping of the shallow epitaxial layer minimizes variations in threshold voltage and local variations in punch-through susceptibility due to nonuniformities in epitaxial doping concentration. A relatively heavily doped epitaxial layer is disposed underneath the shallow lightly doped epitaxial layer to reduce the drain to source resistance, R.sub.DS. Because the relatively heavily doped epitaxial layer is located below the channel region and not in the regions of the structure most susceptible to body region punch-through, providing the relatively highly doped epitaxial layer does not cause variations in threshold voltage and does not cause variations in the reverse bias voltage at which punch-through across the body region occurs.

摘要翻译： 公开了一种低阈值电压功率DMOS晶体管结构，其具有在相对轻掺杂的外延硅的浅层中形成的轻掺杂沟道区。 由于外延掺杂浓度不均匀，浅外延层的掺杂使阈值电压的变化和穿通敏感性的局部变化最小化。 将相对重掺杂的外延层设置在浅掺杂的浅层外延层的下面，以减少漏极 - 源极电阻RDS。 因为相对重掺杂的外延层位于沟道区下方，而不在最易受体区穿透的结构区域内，所以提供相对高掺杂的外延层不会引起阈值电压的变化，并且不会引起变化 出现穿过身体区域穿孔的反向偏置电压。

公开(公告)号：US08159021B2

公开(公告)日：2012-04-17

申请号：US12070853

申请日：2008-02-20

申请人： Fwu-Iuan Hshieh

发明人： Fwu-Iuan Hshieh

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66734

摘要： A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further includes a first epitaxial layer above heavily doped substrate and beyond the trench bottom and a second epitaxial layer above said first epitaxial layer wherein a resistivity N1 of said first epitaxial layer is greater than a resistivity N2 of said second epitaxial layer represented by a functional relationship of N1>N2. In an exemplary embodiment, each of the trenched gates include an upper gate portion and lower gate portion formed with single polysilicon deposition processes wherein the lower gate portion is surrounded with a lower gate insulation layer having a greater thickness than an upper gate insulation layer surrounding the upper gate portion.

摘要翻译： 沟槽半导体功率器件包括被包围在体区域中的半导体衬底的顶表面附近的源极区域包围的多个沟槽栅极。 沟槽半导体功率器件还包括在重掺杂衬底之上并超出沟槽底部的第一外延层和在所述第一外延层上方的第二外延层，其中所述第一外延层的电阻率N1大于所述第二外延层的电阻率N2 由N1> N2的功能关系表示。 在示例性实施例中，每个沟槽栅极包括形成有单个多晶硅沉积工艺的上部栅极部分和下部栅极部分，其中下部栅极部分被下部栅极绝缘层包围，该栅极绝缘层的厚度大于围绕 上门部分。

公开(公告)号：US08022471B2

公开(公告)日：2011-09-20

申请号：US12319188

申请日：2008-12-31

申请人： Fwu-Iuan Hshieh

发明人： Fwu-Iuan Hshieh

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

摘要： A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls.

摘要翻译： 沟槽半导体功率器件包括被包围在体区域中的半导体衬底的顶表面附近的源极区域包围的多个沟槽栅极。 沟槽半导体功率器件还包括围绕沟槽侧壁的下部的倾斜角植入体掺杂区，用于减小沟槽栅极与布置在半导体衬底底部的漏极之间的栅 - 漏耦合电荷Qgd。 沟槽半导体功率器件还包括设置在沟槽栅极的底表面下方的源极掺杂剂区域，用作在漏极到源极之间的电流路径，用于防止由围绕沟槽的下部的体的掺杂剂区域引起的电阻增加 侧壁