公开(公告)号：US08284599B2

公开(公告)日：2012-10-09

申请号：US12786724

申请日：2010-05-25

申请人： Han Woong Yoo ,  Jae Hong Kim ,  Jun Jin Kong

发明人： Han Woong Yoo ,  Jae Hong Kim ,  Jun Jin Kong

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/3427 ,  G11C2211/5648

摘要： A method of programming a nonvolatile memory device comprises programming memory cells connected to a first wordline, programming memory cells connected to a second wordline, programming memory cells connected to a third line between the first wordline and the second wordline, and adjusting a threshold voltage of the memory cells connected to the first wordline to compensate for interference generated by the programming of the memory cells connected to the third wordline.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括编程连接到第一字线的存储器单元，连接到第二字线的编程存储器单元，连接到第一字线和第二字线之间的第三线的编程存储器单元，以及调整阈值电压 连接到第一字线的存储器单元以补偿由连接到第三字线的存储器单元的编程所产生的干扰。

公开(公告)号：US08499217B2

公开(公告)日：2013-07-30

申请号：US12153121

申请日：2008-05-14

申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Sung Chung Park

发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Sung Chung Park

IPC分类号： H03M13/00 ,  G06F11/00 ,  G11C29/00

CPC分类号： G06F11/141 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/10 ,  G11C29/00

摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

公开(公告)号：US08239747B2

公开(公告)日：2012-08-07

申请号：US12216744

申请日：2008-07-10

申请人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

发明人： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC分类号： G06F11/00

CPC分类号： G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

摘要翻译： 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

公开(公告)号：US08085599B2

公开(公告)日：2011-12-27

申请号：US12801505

申请日：2010-06-11

申请人： Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

发明人： Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C29/00 ,  G11C2211/5634

摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

摘要翻译： 提供了可以估计多位单元特性的存储器件和/或方法。 存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。 由此，可以监视存储单元的阈值电压随时间的变化。

公开(公告)号：US07929346B2

公开(公告)日：2011-04-19

申请号：US12216745

申请日：2008-07-10

申请人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

发明人： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

IPC分类号： G11C16/06 ,  G11C16/34 ,  G11C16/26

CPC分类号： G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

摘要： Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

摘要翻译： 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。

公开(公告)号：US07831881B2

公开(公告)日：2010-11-09

申请号：US12230832

申请日：2008-09-05

申请人： Heeseok Eun ,  Jae Hong Kim ,  Jun Jin Kong

发明人： Heeseok Eun ,  Jae Hong Kim ,  Jun Jin Kong

IPC分类号： H04L1/00

CPC分类号： G11C29/52 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5634

摘要： The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

摘要翻译： 数据检测装置可以提供电压比较单元，其将存储在存储单元中的多个数据位中的与特定数据位相关联的参考电压与存储单元中的阈值电压进行比较，检测单元检测 基于电压比较单元的结果的特定数据位的值，以及判定单元，其基于检测到的数据中是否发生错误来判定是否成功检测到特定数据位。 响应于决定的结果，检测单元可以基于关于特定数据比特的上位数据位和下位数据位中的至少一个的检测信息重新检测特定数据位的值 单元。

公开(公告)号：US20100254195A1

公开(公告)日：2010-10-07

申请号：US12801505

申请日：2010-06-11

申请人： Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

发明人： Kyoung Lae Cho ,  Seung-Hwan Song ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/32 ,  G11C16/349 ,  G11C29/00 ,  G11C2211/5634

摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.

摘要翻译： 提供了可以估计多位单元特性的存储器件和/或方法。 存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。 由此，可以监视存储单元的阈值电压随时间的变化。

公开(公告)号：US07738293B2

公开(公告)日：2010-06-15

申请号：US12213944

申请日：2008-06-26

申请人： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

发明人： Kyoung Lae Cho ,  Yoon Dong Park ,  Jun Jin Kong ,  Jong Han Kim ,  Jae Hong Kim ,  Young Hwan Lee ,  Heeseok Eun ,  Seung-Hwan Song

IPC分类号： G11C16/04 ,  G11C29/04

CPC分类号： G11C11/5628 ,  G11C29/00 ,  G11C2216/14

摘要： A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.

摘要翻译： 提供了存储器编程设备和/或方法。 存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。 数据存储单元可以被配置为存储数据页。 第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。 索引存储单元可以被配置为存储所生成的索引信息。 编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。 第一计数单元可以将生成的索引信息发送到编程单元。 存储器编程装置可以监视存储器单元中阈值电压的分布状态。

公开(公告)号：US20090307566A1

公开(公告)日：2009-12-10

申请号：US12475640

申请日：2009-06-01

申请人： Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

发明人： Jong Seon No ,  Beom Kyu Shin ,  Seok Il Youn ,  Jae Dong Yang ,  Jun Jin Kong ,  Jae Hong Kim ,  Yong June Kim ,  Kyoung Lae Cho

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H03M13/1105 ,  H03M13/136 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3738 ,  H03M13/3753 ,  H04L1/0051 ,  H04L1/0057

摘要： An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.

摘要翻译： 公开了一种迭代解码方法，并且包括相对于奇偶校验方程顺序执行多个迭代解码周期，直到奇偶校验方程被解析为止，或者在执行迭代次数期间达到迭代解码周期的最大数量N 解码周期，在数据缓冲器中存储对应于最小数量的位错误的一组可变节点的最小估计值，并且当迭代解码周期数达到时，输出存储在数据缓冲器中的最小估计值作为最终解码结果 N.

公开(公告)号：US20090287975A1

公开(公告)日：2009-11-19

申请号：US12453163

申请日：2009-04-30

申请人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

发明人： Yong June Kim ,  Jae Hong Kim ,  Jun Jin Kong ,  Kyoung Lae Cho

IPC分类号： G06F11/10 ,  G11C16/04 ,  G11C16/06 ,  G11C16/02 ,  H03M13/03

CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

摘要翻译： 提供了存储器件和/或管理存储器数据错误的方法。 存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。 存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。 存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。 由此，可以增加存储装置的数据的保持期。