Method analyzing threshold voltage distribution in nonvolatile memory
    2.
    发明授权
    Method analyzing threshold voltage distribution in nonvolatile memory 有权
    方法分析非易失性存储器中的阈值电压分布

    公开(公告)号:US08116141B2

    公开(公告)日:2012-02-14

    申请号:US12558627

    申请日:2009-09-14

    IPC分类号: G11C11/34

    CPC分类号: G11C16/26 G11C16/3427

    摘要: A distribution analyzing method for a nonvolatile memory device having memory cells exhibiting overlapping first and second threshold voltage distributions includes; detecting a degree of overlap between the first and second threshold voltage distributions by reading data stored in the memory cells and determining read index data from the read data, and estimating a distribution characteristic for at least one of the overlapping threshold voltage distributions using the read index data.

    摘要翻译: 一种具有显示重叠的第一和第二阈值电压分布的存储单元的非易失性存储器件的分布分析方法包括: 通过读取存储在存储单元中的数据并根据读取的数据确定读取的索引数据来检测第一和第二阈值电压分布之间的重叠程度,并且使用读取的索引来估计至少一个重叠阈值电压分布的分布特性 数据。

    Non-Volatile Memory Device and Program Method Thereof
    3.
    发明申请
    Non-Volatile Memory Device and Program Method Thereof 有权
    非易失性存储器件及其程序方法

    公开(公告)号:US20100142281A1

    公开(公告)日:2010-06-10

    申请号:US12575735

    申请日:2009-10-08

    IPC分类号: G11C16/04

    CPC分类号: G11C11/5628 G11C2211/5621

    摘要: Disclosed is a program method of a non-volatile memory device which comprises classifying plural memory cells into aggressor cells and victim cells based on program data to be written in the plural memory cells; and programming the aggressor cells by a program manner different from the victim cells.

    摘要翻译: 本发明公开了一种非易失性存储器件的程序方法,该方法包括:根据要写入多个存储器单元的程序数据,将多个存储单元分为侵略单元和受害单元; 并且通过与受害细胞不同的程序方式对攻击者细胞进行编程。

    Non-volatile memory device and program method thereof
    5.
    发明授权
    Non-volatile memory device and program method thereof 有权
    非易失性存储器件及其程序方法

    公开(公告)号:US08331144B2

    公开(公告)日:2012-12-11

    申请号:US12575735

    申请日:2009-10-08

    IPC分类号: G11C11/34

    CPC分类号: G11C11/5628 G11C2211/5621

    摘要: Disclosed is a program method of a non-volatile memory device which comprises classifying plural memory cells into aggressor cells and victim cells based on program data to be written in the plural memory cells; and programming the aggressor cells by a program manner different from the victim cells.

    摘要翻译: 本发明公开了一种非易失性存储器件的程序方法,该方法包括:根据要写入多个存储器单元的程序数据,将多个存储单元分为侵略单元和受害单元; 并且通过与受害细胞不同的程序方式对攻击者细胞进行编程。

    Access method of non-volatile memory device
    6.
    发明申请
    Access method of non-volatile memory device 有权
    非易失性存储器件的访问方法

    公开(公告)号:US20100149868A1

    公开(公告)日:2010-06-17

    申请号:US12588532

    申请日:2009-10-19

    IPC分类号: G11C16/04

    摘要: Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell.

    摘要翻译: 公开了一种非易失性存储器件的存取方法,包括检测第一存储单元的阈值电压变化,第一存储单元的阈值电压变化能够物理地影响第二存储器单元; 以及根据所述第一存储器单元的阈值电压变化的距离,从所述多个子分布中将所述第二存储器单元分配给所选择的子分布,所述多个子分布对应于所述第二存储器的目标分布 细胞。

    Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same
    7.
    发明授权
    Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same 有权
    在块擦除期间具有内置存储器单元恢复的非易失性存储器件及其操作方法

    公开(公告)号:US08274840B2

    公开(公告)日:2012-09-25

    申请号:US12498508

    申请日:2009-07-07

    IPC分类号: G11C11/34

    CPC分类号: G11C16/16

    摘要: Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

    摘要翻译: 非易失性存储器件包括在擦除非易失性(例如闪存)存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作,该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元,然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

    Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same
    8.
    发明申请
    Nonvolatile Memory Devices Having Built-in Memory Cell Recovery During Block Erase and Methods of Operating Same 有权
    在块擦除期间具有内置存储器单元恢复的非易失性存储器件和操作方法相同

    公开(公告)号:US20100091578A1

    公开(公告)日:2010-04-15

    申请号:US12498508

    申请日:2009-07-07

    IPC分类号: G11C16/04 G11C16/06

    CPC分类号: G11C16/16

    摘要: Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

    摘要翻译: 非易失性存储器件包括在擦除非易失性(例如闪存)存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作,该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元,然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。

    Apparatus for determining number of bits to be stored in memory cell
    9.
    发明申请
    Apparatus for determining number of bits to be stored in memory cell 失效
    用于确定要存储在存储单元中的位数的装置

    公开(公告)号:US20090222701A1

    公开(公告)日:2009-09-03

    申请号:US12219103

    申请日:2008-07-16

    IPC分类号: G06F11/00 G06F12/16

    摘要: Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.

    摘要翻译: 示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置,并且可以基于所确定的长度将数据存储在存储器中。 根据示例实施例的存储器数据存储装置可以包括:确定单元,其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元,其可以接收与所确定的位数相对应的数据; 纠错编码单元,其可以对所接收的数据执行纠错编码,并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元,其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

    Memory device and method of reading memory data
    10.
    发明申请
    Memory device and method of reading memory data 有权
    存储器件和读取存储器数据的方法

    公开(公告)号:US20090190396A1

    公开(公告)日:2009-07-30

    申请号:US12219264

    申请日:2008-07-18

    IPC分类号: G11C16/06 G11C7/00

    摘要: A memory device and a method of reading multi-bit data stored in a multi-bit cell array may be provided. The memory device may include a multi-bit cell array including a least one memory page with each memory page having a plurality of multi-bit cells, and a determination unit to divide the plurality of multi-bit cells into a first group and second group. The first group may include multi-bit cells with a threshold voltage higher than a reference voltage. The second group may include multi-bit cells with a threshold voltage lower than the reference voltage. The determination unit may sequentially update the first group and second group while changing the reference voltage.

    摘要翻译: 可以提供存储器件和读取存储在多位单元阵列中的多位数据的方法。 存储器件可以包括多比特单元阵列,其包括至少一个存储器页,每个存储器页具有多个多位单元,以及确定单元,用于将多个多位单元划分成第一组和第二组 。 第一组可以包括具有高于参考电压的阈值电压的多位单元。 第二组可以包括阈值电压低于参考电压的多位单元。 确定单元可以在改变参考电压的同时顺序地更新第一组和第二组。