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    Methods of compressing data in storage device
    2.
    发明授权
    Methods of compressing data in storage device 有权
    在存储设备中压缩数据的方法

    公开(公告)号：US08593307B2

    公开(公告)日：2013-11-26

    申请号：US13364787

    申请日：2012-02-02

    申请人： Man-keun Seo ,  Jun-jin Kong ,  Hong-rak Son ,  Kyoung-Lae Cho ,  Je-hyuck Song ,  Kwang-gu Lee

    发明人： Man-keun Seo ,  Jun-jin Kong ,  Hong-rak Son ,  Kyoung-Lae Cho ,  Je-hyuck Song ,  Kwang-gu Lee

    IPC分类号： H03M7/40

    CPC分类号： H03M7/40

    摘要： At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

    摘要翻译： 至少一个示例性实施例公开了一种在存储设备中压缩数据的方法。 该方法包括使用指示接收数据中的符号的出现次数与码字长度之间的关系的第一表来确定符号的码字长度，确定具有用于符号的码字长度的码字，以及生成 接收到的数据，生成包括将符号转换成码字。

    Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device
    3.
    发明授权
    Non-volatile memory device, operation method thereof, and devices having the non-volatile memory device 有权
    非易失性存储器件，其操作方法以及具有非易失性存储器件的器件

    公开(公告)号：US08508990B2

    公开(公告)日：2013-08-13

    申请号：US13071727

    申请日：2011-03-25

    申请人： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

    发明人： Kyoung Lae Cho ,  Hyuck-Sun Kwon ,  Jun Jin Kong

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C16/3454

    摘要： A non-volatile memory device includes a memory cell array including a plurality of multi-level cells each storing data corresponding to one of a plurality of states of a first group of states, and a control circuit. The control circuit is configured to program data corresponding to one of the plurality of states in a first multi-level cell according to a first verify voltage level of a first group of verify voltage levels, and to control the first multi-level cell to be re-programmed to one of a plurality of states of a second group of states according to a first verify voltage level of a second group of verify voltage levels. Each voltage level of the second group of verify voltage levels has a higher level than the verify voltage levels of the first group of verify voltage levels.

    摘要翻译： 非易失性存储器件包括存储单元阵列，该存储单元阵列包括多个多电平单元，每个多电平单元存储对应于第一组状态的多种状态之一的数据，以及控制电路。 控制电路被配置为根据第一组验证电压电平的第一验证电压电平对与第一多电平单元中的多个状态中的一个状态相对应的数据，并且将第一多电平单元控制为 根据第二组验证电压电平的第一验证电压电平，将其重新编程为第二组状态的多个状态之一。 第二组验证电压电平的每个电压电平具有比第一组验证电压电平的验证电压电平更高的电平。

    Memory system with error correction decoder architecture having reduced latency and increased throughput
    4.
    发明授权
    Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
    具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量

    公开(公告)号：US08479085B2

    公开(公告)日：2013-07-02

    申请号：US12191458

    申请日：2008-08-14

    申请人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。

    MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND CONTROLLING METHOD OF CONTROLLING NONVOLATILE MEMORY DEVICE
    5.
    发明申请
    MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND CONTROLLING METHOD OF CONTROLLING NONVOLATILE MEMORY DEVICE 审中-公开
    包括非易失性存储器件的存储器系统和控制非易失性存储器件的控制方法

    公开(公告)号：US20130117635A1

    公开(公告)日：2013-05-09

    申请号：US13550980

    申请日：2012-07-17

    申请人： Dong Ju Ok ,  Kyoung Lae Cho ,  Dongsub Kim

    发明人： Dong Ju Ok ,  Kyoung Lae Cho ,  Dongsub Kim

    IPC分类号： G06F12/00 ,  G06F11/16

    CPC分类号： G06F11/1048 ,  G11C16/00 ,  G11C29/021 ,  G11C29/028

    摘要： Disclosed is a method of controlling a nonvolatile memory device which includes programming data in a user data area of the nonvolatile memory device and state information on logical states of the data in a meta area of the nonvolatile memory device; and adjusting levels of a plurality of read voltages using the state information to read the data from the user data area using the plurality of read voltages having the adjusted levels.

    摘要翻译： 本发明公开了一种非易失性存储器件的控制方法，其包括非易失性存储器件的用户数据区域中的数据编程和非易失性存储器件的元区域中的数据的逻辑状态的状态信息; 以及使用所述状态信息来调整多个读取电压的电平，以使用具有所述调整电平的所述多个读取电压从所述用户数据区域读取数据。

    DATA COMPRESSION METHOD
    6.
    发明申请
    DATA COMPRESSION METHOD 审中-公开
    数据压缩方法

    公开(公告)号：US20130060992A1

    公开(公告)日：2013-03-07

    申请号：US13598871

    申请日：2012-08-30

    申请人： KYOUNG-LAE CHO ,  JUN-JIN KONG

    发明人： KYOUNG-LAE CHO ,  JUN-JIN KONG

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/401 ,  G06F2212/7202

    摘要： A data compression method includes; generating compressed data from raw data having a normal size, defining a super page for a memory having a super size greater than the normal size, selecting a compressed data set from among the compressed data having a compression ratio less than a reference compression ratio ranging between 0.5 and 1.0, and storing the compressed data set in the memory using the super page.

    摘要翻译： 数据压缩方法包括： 从具有正常大小的原始数据生成压缩数据，为具有超过正常大小的超大尺寸的存储器定义超级页面，从压缩数据中选择压缩数据集，压缩数据的压缩数据小于 0.5和1.0，并且使用超级页面将压缩数据集存储在存储器中。

    METHODS OF COMPRESSING DATA IN STORAGE DEVICE
    9.
    发明申请
    METHODS OF COMPRESSING DATA IN STORAGE DEVICE 有权
    存储设备中压缩数据的方法

    公开(公告)号：US20120242517A1

    公开(公告)日：2012-09-27

    申请号：US13364787

    申请日：2012-02-02

    申请人： Man-keun SEO ,  Jun-jin KONG ,  Hong-rak SON ,  Kyoung-Lae CHO ,  Je-hyuck SONG ,  Kwang-gu LEE

    发明人： Man-keun SEO ,  Jun-jin KONG ,  Hong-rak SON ,  Kyoung-Lae CHO ,  Je-hyuck SONG ,  Kwang-gu LEE

    IPC分类号： H03M5/00

    CPC分类号： H03M7/40

    摘要： At least one example embodiment discloses a method of compressing data in a storage device. The method includes determining a codeword length of a symbol using a first table indicating a relationship between a number of occurrences of the symbol in received data and the codeword length, determining a codeword having the codeword length for the symbol, and generating compressed data of the received data, the generating including converting the symbol into the codeword.

    摘要翻译： 至少一个示例性实施例公开了一种在存储设备中压缩数据的方法。 该方法包括使用指示接收数据中的符号的出现次数与码字长度之间的关系的第一表来确定符号的码字长度，确定具有用于符号的码字长度的码字，以及生成 接收到的数据，生成包括将符号转换成码字。

    Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same
    10.
    发明授权
    Nonvolatile memory devices having built-in memory cell recovery during block erase and methods of operating same 有权
    在块擦除期间具有内置存储器单元恢复的非易失性存储器件及其操作方法

    公开(公告)号：US08274840B2

    公开(公告)日：2012-09-25

    申请号：US12498508

    申请日：2009-07-07

    申请人： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

    发明人： Yong-June Kim ,  Jae-Hong Kim ,  Kyoung-Lae Cho ,  Seung-Hwan Song ,  Jun-Jin Kong

    IPC分类号： G11C11/34

    CPC分类号： G11C16/16

    摘要： Nonvolatile memory devices include support memory cell recovery during operations to erase blocks of nonvolatile (e.g., flash) memory cells. A nonvolatile memory system includes a flash memory device and a memory controller electrically coupled to the flash memory device. The memory controller is configured to control memory cell recovery operations within the flash memory device by issuing a first instruction(s) to the flash memory device that causes erased memory cells in the block of memory to become at least partially programmed memory cells and then issuing a second instruction(s) to the flash memory device that causes the at least partially programmed memory cells become fully erased.

    摘要翻译： 非易失性存储器件包括在擦除非易失性（例如闪存）存储器单元块的操作期间的支持存储器单元恢复。 非易失性存储器系统包括闪存器件和电耦合到闪速存储器件的存储器控​​制器。 存储器控制器被配置为通过向闪存器件发出第一指令来控制闪存器件内的存储器单元恢复操作，该第一指令使存储器块中的擦除存储器单元变成至少部分被编程的存储器单元，然后发出 使闪存器件的至少部分编程的存储器单元完全被擦除的第二指令。