公开(公告)号：US08503230B2

公开(公告)日：2013-08-06

申请号：US12588532

申请日：2009-10-19

申请人： Han Woong Yoo ,  KyoungLae Cho ,  Seung-Hwan Song ,  Heeseok Eun ,  Hong Rak Son

发明人： Han Woong Yoo ,  KyoungLae Cho ,  Seung-Hwan Song ,  Heeseok Eun ,  Hong Rak Son

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell.

摘要翻译： 公开了一种非易失性存储器件的存取方法，包括检测第一存储单元的阈值电压变化，第一存储单元的阈值电压变化能够物理地影响第二存储器单元; 以及根据所述第一存储器单元的阈值电压变化的距离，从所述多个子分布中将所述第二存储器单元分配给所选择的子分布，所述多个子分布对应于所述第二存储器的目标分布 细胞。

公开(公告)号：US20100149868A1

公开(公告)日：2010-06-17

申请号：US12588532

申请日：2009-10-19

申请人： Han Woong Yoo ,  KyoungLae Cho ,  Seung-Hwan Song ,  Heeseok Eun ,  Hong Rak Son

发明人： Han Woong Yoo ,  KyoungLae Cho ,  Seung-Hwan Song ,  Heeseok Eun ,  Hong Rak Son

IPC分类号： G11C16/04

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Disclosed is an access method of a non-volatile memory device which comprises detecting a threshold voltage variation of a first memory cell, the a threshold voltage variation of the first memory cell being capable of physically affecting a second memory cell; and assigning the second memory cell to a selected sub-distribution from among a plurality of sub-distributions according to a distance of the threshold voltage variation of the first memory cell, the plurality of sub-distributions corresponding to a target distribution of the second memory cell.

摘要翻译： 公开了一种非易失性存储器件的存取方法，包括检测第一存储单元的阈值电压变化，第一存储单元的阈值电压变化能够物理地影响第二存储器单元; 以及根据所述第一存储器单元的阈值电压变化的距离，从所述多个子分布中将所述第二存储器单元分配给所选择的子分布，所述多个子分布对应于所述第二存储器的目标分布 细胞。

公开(公告)号：US20100302850A1

公开(公告)日：2010-12-02

申请号：US12662329

申请日：2010-04-12

申请人： Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

发明人： Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

IPC分类号： G11C16/06 ,  G11C7/10 ,  G11C16/04

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/00

摘要： The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution.

摘要翻译： 存储装置包括：被配置为存储数据的存储单元;错误控制单元，被配置为根据至少一个读取级别校正从存储单元读出的数据的错误;以及读取级别控制单元，被配置为至少控制 一个读取级别，当错误是不可校正的。 读取级别控制单元被配置为测量存储单元的存储器单元的分布，被配置为过滤所测量的分布，并且被配置为基于滤波的分布来重置所述至少一个读取级别。

公开(公告)号：US08422291B2

公开(公告)日：2013-04-16

申请号：US12662329

申请日：2010-04-12

申请人： Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

发明人： Yong June Kim ,  Heeseok Eun ,  Han Woong Yoo ,  Jaehong Kim ,  Hong Rak Son

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/0483 ,  G11C29/00

摘要： The storage device includes a storage unit configured to store data, an error controlling unit configured to correct an error of the data read out from the storage unit according to at least one read level, and a read level controlling unit configured to control the at least one read level when the error is uncorrectable. The read level controlling unit is configured to measure a distribution of memory cells of the storage unit, configured to filter the measured distribution, and configured to reset the at least one read level based on the filtered distribution.

摘要翻译： 存储装置包括：被配置为存储数据的存储单元;错误控制单元，被配置为根据至少一个读取级别校正从存储单元读出的数据的错误;以及读取级别控制单元，被配置为至少控制 一个读取级别，当错误是不可校正的。 读取级别控制单元被配置为测量存储单元的存储器单元的分布，被配置为过滤所测量的分布，并且被配置为基于滤波的分布来重置所述至少一个读取级别。

公开(公告)号：US20110249496A1

公开(公告)日：2011-10-13

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/10

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。

公开(公告)号：US08441862B2

公开(公告)日：2013-05-14

申请号：US13080809

申请日：2011-04-06

申请人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

发明人： Hong Rak Son ,  Han Woong Yoo ,  Jaehong Kim ,  Jun Jin Kong

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3436

摘要： Provided is a program method of a multi-bit memory device with memory cells arranged in rows and columns. The program method includes a programming each memory cell of the first group of memory cells to a state within a first group of states according to a verify voltage level of a first group of verify voltage levels within a first range of levels, and programming each memory cell of the second group of memory cells to a state within a second group of states according to a verify voltage level of a second group of verify voltage levels within a second range of levels. The lowest verify voltage level in the second range of levels is higher than the highest verify voltage level in the first range of levels. A first voltage difference between adjacent verify voltage levels within the first range of levels is different from a second voltage difference between the highest verify voltage level of the second group of verify voltage levels and the lowest verify voltage level of the third group of verify voltage levels.

摘要翻译： 提供了具有排列成行和列的存储单元的多位存储器件的编程方法。 程序方法包括根据第一级别的第一组验证电压电平的验证电压电平将第一组存储器单元的每个存储器单元编程到第一组状态内的状态，以及编程每个存储器 第二组存储器单元的单元根据在第二级别范围内的第二组验证电压电平的验证电压电平而处于第二组状态内的状态。 第二级别的最低验证电压电平高于第一级别范围内的最高验证电压电平。 在第一级别范围内的相邻验证电压电平之间的第一电压差不同于第二组验证电压电平的最高验证电压电平与第三组验证电压电平的最低验证电压电平之间的第二电压差 。

公开(公告)号：US20120257455A1

公开(公告)日：2012-10-11

申请号：US13211743

申请日：2011-08-17

申请人： Eun Chu Oh ,  Hong Rak Son ,  KyoungLae Cho ,  Junjin Kong

发明人： Eun Chu Oh ,  Hong Rak Son ,  KyoungLae Cho ,  Junjin Kong

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3454

摘要： Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.

摘要翻译： 操作包括多个单元串的非易失性存储器件的方法，每个单元串具有至少一个接地选择晶体管，多个存储单元和至少一个串选择晶体管，所述操作方法包括接收命令和地址，确定施加的电压 响应于输入命令和地址的时间，以及在确定的电压施加时间期间，将特定电压施加到对应于输入地址的单元串的存储单元。

公开(公告)号：US08751900B2

公开(公告)日：2014-06-10

申请号：US13106892

申请日：2011-05-13

申请人： Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

发明人： Yong June Kim ,  Hong Rak Son ,  Seonghyeog Choi ,  Junjin Kong ,  Yongtaew Yim ,  Jaehong Kim ,  KyoungLae Cho ,  Wootae Chang

IPC分类号： G11C29/00 ,  H03M13/00

CPC分类号： G06F11/106 ,  H03M13/1102 ,  H03M13/136 ,  H03M13/152 ,  H03M13/155 ,  H03M13/2909 ,  H03M13/618

摘要： A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.

摘要翻译： 存储装置包括从源区域输出读取数据的非易失性存储器装置和被配置为对读取数据中的多个向量执行ECC操作并将经纠错的读取数据写入到目标区域中的存储器控​​制器 非易失性存储器件。 存储器控制器声明对应于清洁区域的矢量是在纠错操作期间不使用多个矢量中的标志位的解码通过。

公开(公告)号：US08730738B2

公开(公告)日：2014-05-20

申请号：US13211743

申请日：2011-08-17

申请人： Eun Chu Oh ,  Hong Rak Son ,  KyoungLae Cho ,  Junjin Kong

发明人： Eun Chu Oh ,  Hong Rak Son ,  KyoungLae Cho ,  Junjin Kong

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3454

摘要： Methods of operating nonvolatile memory devices including a plurality of cell strings each having at least one ground selection transistor, a plurality of memory cells, and at least one string selection transistor, the operating methods including receiving a command and an address, determining a voltage applying time in response to the input command and address, and applying a specific voltage to memory cells of cell strings corresponding to the input address during the determined voltage applying time.

摘要翻译： 操作包括多个单元串的非易失性存储器件的方法，每个单元串具有至少一个接地选择晶体管，多个存储单元和至少一个串选择晶体管，所述操作方法包括接收命令和地址，确定施加的电压 响应于输入命令和地址的时间，以及在确定的电压施加时间期间，将特定电压施加到对应于输入地址的单元串的存储单元。

公开(公告)号：US08711624B2

公开(公告)日：2014-04-29

申请号：US13236249

申请日：2011-09-19

申请人： Seonghyeog Choi ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

发明人： Seonghyeog Choi ,  Hong Rak Son ,  Junjin Kong ,  Jaehong Kim ,  KyoungLae Cho ,  Yong June Kim

IPC分类号： G11C11/34

CPC分类号： G11C11/5621 ,  G11C16/10 ,  G11C16/3404

摘要： A memory device includes a memory cell array, a self interleaver configured to interleave and load data on the fly into a buffer circuit using an interleaving scheme, and a control logic configured to control programming of the interleaved data in the memory cell array.

摘要翻译： 存储器装置包括存储单元阵列，配置成使用交织方案将数据进行交错和加载到缓冲电路中的自交织器以及被配置为控制对存储单元阵列中的交错数据的编程的控制逻辑。