公开(公告)号：US5787039A

公开(公告)日：1998-07-28

申请号：US812615

申请日：1997-03-06

申请人： Han-Sung Chen ,  Tzeng-Huei Shiau ,  Yu-Shen Lin ,  Chung-Cheng Tsai ,  Jin-Lien Lin ,  Ray Lin Wan ,  Yuan-Chang Liu ,  Chun Hsiung Hung

发明人： Han-Sung Chen ,  Tzeng-Huei Shiau ,  Yu-Shen Lin ,  Chung-Cheng Tsai ,  Jin-Lien Lin ,  Ray Lin Wan ,  Yuan-Chang Liu ,  Chun Hsiung Hung

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/3486 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/3468

摘要： A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.

摘要翻译： 用于编程浮动栅极存储器单元阵列的系统减少了编程电流要求，并且减少了编程期间的字线和位线应力。 要被编程到浮动存储器阵列中的字被分成多个较小的子字。 一次只编写一个子字，从而减少编程电流的要求。 此外，即使其他子词的位未正确编程，成功编程的子词也不会被重新编程。 这与以前系统一样编制整个单词的系统产生较少的字面压力，从而要求程序成功地重新编程的子词以及不能编程的子词。 最后，在每个子字中，只有那些无法编程的位被重新编程，从而在对已成功编程的那些位的重新编程期间减少位线应力。

公开(公告)号：US08405536B2

公开(公告)日：2013-03-26

申请号：US13329751

申请日：2011-12-19

申请人： Ting-Yuan Cheng ,  Jin-Lien Lin ,  Shih-Hsien Yang

发明人： Ting-Yuan Cheng ,  Jin-Lien Lin ,  Shih-Hsien Yang

IPC分类号： H03M1/12

CPC分类号： H04L27/122

摘要： A communication system includes a time-to-digital converter, a digital low-pass filter, and a digital signal processor. The time-to-digital converter receives an in-phase signal of a frequency-shift keying signal and to generate a digital signal according to the in-phase signal. The digital low-pass filter receives the digital signal and to generate a filtered signal including N continuous words according to the digital signal. The digital signal processor divides up the N continuous words into N/2 word sets in order, wherein each of the N/2 word sets includes a first word and a second word, and if a difference between the first word and the second word meets a predetermined condition, the digital signal processor generates an output data and an output clock according to all the first words and the second words that have difference which meets the predetermined condition.

摘要翻译： 通信系统包括时间 - 数字转换器，数字低通滤波器和数字信号处理器。 时间 - 数字转换器接收频移键控信号的同相信号，并根据同相信号产生数字信号。 数字低通滤波器接收数字信号并根据数字信号产生包括N个连续字的滤波信号。 数字信号处理器按顺序将N个连续字分成N / 2个字组，其中N / 2个字组中的每一个包括第一个字和第二个字，并且如果第一个字和第二个字之间的差值满足 在预定条件下，数字信号处理器根据满足预定条件的所有第一个字和第二个字产生一个输出数据和一个输出时钟。

公开(公告)号：US08289008B2

公开(公告)日：2012-10-16

申请号：US12726340

申请日：2010-03-17

申请人： Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

发明人： Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

IPC分类号： G05F1/40

CPC分类号： G05F1/563 ,  G05F1/575

摘要： A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

摘要翻译： 电压调节器包括放大器，功率器件，延迟信号发生器和产生电压的电路。 放大器根据参考电压和反馈电压产生控制信号。 电源开关通过根据开关控制信号调节输出电流来产生输出电压。 延迟信号发生器产生多个相对于外部施加的上电突发信号具有不同延迟时间的顺序延迟信号。 电压产生电路提供用于产生对应于输出电压的反馈电压的等效电阻，并且通过根据多个顺序延迟信号调整等效电阻来调节输出电压。

公开(公告)号：US06507527B1

公开(公告)日：2003-01-14

申请号：US09698614

申请日：2000-10-27

申请人： Lee Cleveland ,  Jin-Lien Lin ,  Takao Akaogi ,  Ali Al-Shamma ,  Boon Tang Teh ,  Kendra Nguyen ,  Yong Kim

发明人： Lee Cleveland ,  Jin-Lien Lin ,  Takao Akaogi ,  Ali Al-Shamma ,  Boon Tang Teh ,  Kendra Nguyen ,  Yong Kim

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/12

摘要： A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

摘要翻译： 一种通过将数据线从高于期望电压电平的电压电平放电到大约期望的电压电平，在数据线在低功率存储器件中被感测之前将数据线充电到期望的电压电平的方法。 通过使用N型晶体管将数据线放电至期望的电压电平，可以用更便宜的组件更快地达到电压电平。

公开(公告)号：US5781473A

公开(公告)日：1998-07-14

申请号：US720944

申请日：1996-10-04

申请人： Jahanshir J. Javanifard ,  Kerry D. Tedrow ,  Jin-Lien Lin ,  Jeffrey J. Evertt ,  Gregory E. Atwood

发明人： Jahanshir J. Javanifard ,  Kerry D. Tedrow ,  Jin-Lien Lin ,  Jeffrey J. Evertt ,  Gregory E. Atwood

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H02M3/07 ,  H02M3/28 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/07 ,  H02M2001/007 ,  H02M3/285

摘要： A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pump are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

摘要翻译： 描述了一种用于闪存器件的可变级电荷泵。 可变级电荷泵包括第一电荷泵和第二电荷泵。 第一开关将第一电荷泵的输出耦合到第二电荷泵的输入端。 第二开关将第一电荷泵的输入耦合到第二电荷泵的输入端。 当第一开关处于第一位置并且第二开关处于第二位置时，第一和第二电荷泵串联耦合到公共输出节点，其中第一和第二电荷泵并联耦合到公共输出节点 当第一开关处于第二位置并且第二开关处于第一位置时。

公开(公告)号：US5732039A

公开(公告)日：1998-03-24

申请号：US720876

申请日：1996-10-03

申请人： Jahanshir J. Javanifard ,  Kerry D. Tedrow ,  Jin-Lien Lin ,  Jeffrey J. Evertt ,  Gregory E. Atwood

发明人： Jahanshir J. Javanifard ,  Kerry D. Tedrow ,  Jin-Lien Lin ,  Jeffrey J. Evertt ,  Gregory E. Atwood

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H02M3/07 ,  H02M3/28 ,  H01L7/089 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/07 ,  H02M2001/007 ,  H02M3/285

摘要： A variable stage charge pump for a flash memory device is described. The variable stage charge pump includes a first charge pump and a second charge pump. A first switch couples an output of the first charge pump to an input of the second charge pump. A second switch couples an input of the first charge pump to the input of the second charge pump. The first and second charge pumps are series-coupled to a common output node when the first switch is in a first position and the second switch is in a second position, wherein the first and second charge pumps are parallel-coupled to the common output node when the first switch is in the second position and the second switch is in the first position.

公开(公告)号：US20120326908A1

公开(公告)日：2012-12-27

申请号：US13329751

申请日：2011-12-19

申请人： Ting-Yuan Cheng ,  Jin-Lien Lin ,  Shih-Hsien Yang

发明人： Ting-Yuan Cheng ,  Jin-Lien Lin ,  Shih-Hsien Yang

IPC分类号： H03M1/12

CPC分类号： H04L27/122

摘要： A communication system includes a time-to-digital converter, a digital low-pass filter, and a digital signal processor. The time-to-digital converter receives an in-phase signal of a frequency-shift keying signal and to generate a digital signal according to the in-phase signal. The digital low-pass filter receives the digital signal and to generate a filtered signal including N continuous words according to the digital signal. The digital signal processor divides up the N continuous words into N/2 word sets in order, wherein each of the N/2 word sets includes a first word and a second word, and if a difference between the first word and the second word meets a predetermined condition, the digital signal processor generates an output data and an output clock according to all the first words and the second words that have difference which meets the predetermined condition.

摘要翻译： 通信系统包括时间 - 数字转换器，数字低通滤波器和数字信号处理器。 时间 - 数字转换器接收频移键控信号的同相信号，并根据同相信号产生数字信号。 数字低通滤波器接收数字信号并根据数字信号产生包括N个连续字的滤波信号。 数字信号处理器按顺序将N个连续字分成N / 2个字组，其中N / 2个字组中的每一个包括第一个字和第二个字，并且如果第一个字和第二个字之间的差值满足 在预定条件下，数字信号处理器根据满足预定条件的所有第一个字和第二个字产生一个输出数据和一个输出时钟。

公开(公告)号：US20110156667A1

公开(公告)日：2011-06-30

申请号：US12726340

申请日：2010-03-17

申请人： Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

发明人： Jui-Yu Chang ,  Chih-Wei Chen ,  Jin-Lien Lin

IPC分类号： G05F1/00

CPC分类号： G05F1/563 ,  G05F1/575

摘要： A voltage regulator includes an amplifier, a power device, a delay signal generator, and a voltage-generating circuit. The amplifier generates a control signal according to a reference voltage and a feedback voltage. The power switch generates the output voltage by regulating the output current according to the switch control signal. The delay signal generator generates a plurality of sequential delay signals each having distinct delay time with respect to an externally applied power-on burst signal. The voltage-generating circuit provides an equivalent resistance for generating the feedback voltage corresponding to the output voltage, and regulates the output voltage by adjusting the equivalent resistance according to the plurality of sequential delay signals.

摘要翻译： 电压调节器包括放大器，功率器件，延迟信号发生器和产生电压的电路。 放大器根据参考电压和反馈电压产生控制信号。 电源开关通过根据开关控制信号调节输出电流来产生输出电压。 延迟信号发生器产生多个相对于外部施加的上电突发信号具有不同延迟时间的顺序延迟信号。 电压产生电路提供用于产生对应于输出电压的反馈电压的等效电阻，并且通过根据多个顺序延迟信号调整等效电阻来调节输出电压。

公开(公告)号：US20100008620A1

公开(公告)日：2010-01-14

申请号：US12170570

申请日：2008-07-10

申请人： Shih-Cheng Chang ,  Jin-Lien Lin ,  Kuo-Ching Hsu ,  Kai-Ming Ching ,  Jiun Yi Wu ,  Yen-Huei Chen

发明人： Shih-Cheng Chang ,  Jin-Lien Lin ,  Kuo-Ching Hsu ,  Kai-Ming Ching ,  Jiun Yi Wu ,  Yen-Huei Chen

IPC分类号： G02B6/12

CPC分类号： G02B6/43 ,  G06F1/105

摘要： An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.

摘要翻译： 集成电路结构包括：包括前表面和后表面的半导体芯片; 从半导体芯片的背面延伸到半导体芯片的通孔，其中所述通孔是透光的; 和半导体芯片中的光子检测器，并暴露于通孔。

公开(公告)号：US5999451A

公开(公告)日：1999-12-07

申请号：US114695

申请日：1998-07-13

申请人： Jin-Lien Lin ,  I-Long Lee

发明人： Jin-Lien Lin ,  I-Long Lee

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10

摘要： In a floating gate memory that has a buffer that can be coupled to a set of floating gate memory cells in the memory, a method of writing to a selected portion of the set of floating gate cells. For example, a method of writing a byte to a floating gate memory where the memory uses a page buffer reads and writes to an entire row of cells at a time. Store contents of the set of floating gate cells into the buffer, store the data into a portion of the buffer corresponding to the selected portion of the set of floating gate cells, and store contents of the buffer into the set of floating gate cells. An improved floating gate memory is disclosed in which data may be loaded into a portion of the floating gate cells in a set of cells that may be coupled to a buffer.

摘要翻译： 在具有可以耦合到存储器中的一组浮动栅极存储器单元的缓冲器的浮动存储器中，写入到该浮动栅极单元组的选定部分的方法。 例如，将字节写入浮动存储器的方法，其中存储器使用页缓冲器一次读取和写入整个单元行。 将该组浮动单元的内容存储到缓冲器中，将数据存储到与该浮置单元组的所选部分相对应的缓冲器的一部分中，并将该缓冲器的内容存储到该浮动单元组中。 公开了一种改进的浮动栅极存储器，其中可以将数据加载到可以耦合到缓冲器的一组单元中的浮动栅极单元的一部分中。