公开(公告)号：US5053346A

公开(公告)日：1991-10-01

申请号：US495951

申请日：1990-03-20

申请人： Han-Tzong Yuan ,  Liem Th Tran

发明人： Han-Tzong Yuan ,  Liem Th Tran

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/7327 ,  H01L29/7371 ,  Y10S148/011

摘要： Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced. This in turn reduces the capacitance associated with this junction and correspondingly improves device operating speed. By forming a portion of the collector in the trench, the lateral dimensions of the transistor may be reduced and higher levels of device integration are made possible.

摘要翻译： 在砷化镓衬底中制造具有大大降低的发射极到基极结面积和集电极尺寸的垂直埋地发射极异质结双极晶体管，以形成集成电路结构。 通过沿着已经在层状砷化镓结构的上两层中蚀刻的沟槽的侧壁和底部形成基底的一部分来实现缩放这些临界尺寸的能力。 基底通过将铍注入上层的表面，形成在未掺杂层中的沟槽侧壁和形成在掩埋发射体上的未掺杂层的沟槽的底部而形成。 具有减小的横向尺寸的GaAs集电极层沉积在沟槽中并且部分地沉积在分层结构的表面上。 由于基极区域的一小部分（沟槽的底部）与重掺杂的发射极层直接接触，所以发射极到基极结面积可以显着降低。 这反过来又降低了与该结点相关联的电容，并相应地提高了器件的工作速度。 通过在沟槽中形成集电极的一部分，可以减小晶体管的横向尺寸，使得可以实现更高水平的器件集成。

公开(公告)号：US4956689A

公开(公告)日：1990-09-11

申请号：US462926

申请日：1990-01-12

申请人： Han-Tzong Yuan ,  Liem Th. Tran

发明人： Han-Tzong Yuan ,  Liem Th. Tran

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/7327 ,  H01L29/7371

摘要： Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced. This in turn reduces the capacitance associated with this junction and correspondingly improves device operating speed. By forming a portion of the collector in the trench, the lateral dimensions of the transistor may be reduced and higher levels of device integration are made possible.

摘要翻译： 在砷化镓衬底中制造具有大大降低的发射极到基极结面积和集电极尺寸的垂直埋地发射极异质结双极晶体管，以形成集成电路结构。 通过沿着已经在层状砷化镓结构的上两层中蚀刻的沟槽的侧壁和底部形成基底的一部分来实现缩放这些临界尺寸的能力。 基底通过将铍注入上层的表面，形成在未掺杂层中的沟槽侧壁和形成在掩埋发射体上的未掺杂层的沟槽的底部而形成。 具有减小的横向尺寸的GaAs集电极层沉积在沟槽中并且部分地沉积在分层结构的表面上。 由于基极区域的一小部分（沟槽的底部）与重掺杂的发射极层直接接触，所以发射极到基极结面积可以显着降低。 这反过来又降低了与该结点相关联的电容，并相应地提高了器件的工作速度。 通过在沟槽中形成集电极的一部分，可以减小晶体管的横向尺寸，使得可以实现更高水平的器件集成。

公开(公告)号：US5407842A

公开(公告)日：1995-04-18

申请号：US255502

申请日：1994-06-08

申请人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

发明人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

IPC分类号： H01L21/331 ,  H01L27/06 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  H01L27/0605 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/072

摘要： This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.

摘要翻译： 这是一种形成双极晶体管的方法，包括：在衬底上形成具有掺杂类型和掺杂水平的子集电极层; 在子集电极层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第一层; 增加第一层的第一和第二区域的掺杂水平; 在第一层上形成与子集电极层相同的掺杂类型和较低掺杂水平的第二层; 增加在第一层的第一区域之上的第二层的第一区域的掺杂水平，由此子集电极层，第一层的第一区域和第二层的第一区域是晶体管的集电极; 在与所述子集电极层相反的掺杂类型的第二层上形成基底层; 并且在基底层上形成与子集电极层相同的掺杂类型的发射极层。 还公开了其它装置和方法。

公开(公告)号：US5290719A

公开(公告)日：1994-03-01

申请号：US956132

申请日：1992-10-02

申请人： Han-Tzong Yuan ,  Hisashi Shichijo ,  Hung-Dah Shih

发明人： Han-Tzong Yuan ,  Hisashi Shichijo ,  Hung-Dah Shih

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L27/095 ,  H01L29/43 ,  H01L29/778 ,  H01L21/265

CPC分类号： H01L21/8252 ,  H01L27/0605 ,  H01L27/095 ,  H01L29/432 ,  H01L29/7786 ,  Y10S148/072

摘要： Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopants to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

摘要翻译： 公开了具有互补栅极（40,50）和阈值调节掺杂的互补器件的互补异质结构场效应晶体管（30）。 优选实施例的器件包括由掺杂剂扩散形成的p +栅极（50），以将n +栅极材料转换为p +，以及与二维载气通道相邻的脉冲掺杂层以调整阈值电压。 进一步优选的实施例具有包含未转换的n +的残留层的导电型转换栅极（50），其与脉冲掺杂层阈值移位配合，以产生对n沟道小且为正的阈值电压， 通道设备。

公开(公告)号：US5214298A

公开(公告)日：1993-05-25

申请号：US582818

申请日：1990-09-14

申请人： Han-Tzong Yuan ,  Hisashi Shichijo ,  Hung-Dah Shih

发明人： Han-Tzong Yuan ,  Hisashi Shichijo ,  Hung-Dah Shih

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L27/095 ,  H01L29/43 ,  H01L29/778

CPC分类号： H01L21/8252 ,  H01L27/0605 ,  H01L27/095 ,  H01L29/432 ,  H01L29/7786 ,  Y10S148/072

摘要： Complementary heterostructure field effect transistors (30) with complementary devices having complementary gates (40, 50) and threshold adjusting dopings are disclosed. Preferred embodiment devices include a p.sup.+ gate (50) formed by diffusion of dopant to convert n.sup.+ gate material to p.sup.+, and a pulse-doped layer adjacent the two-dimensional carrier gas channels to adjust threshold voltages. Further preferred embodiments have the conductivity-type converted gate (50) containing a residual layer of unconverted n.sup.+ which cooperates with the pulse-doped layer threshold shifting to yield threshold voltages which are small and positive for n-channel and small and negative for p-channel devices.

摘要翻译： 公开了具有互补栅极（40,50）和阈值调整掺杂的互补器件的互补异质结构场效应晶体管（30）。 优选实施例的器件包括通过掺杂剂的扩散将n +栅极材料转化为p +形成的p +栅极（50）以及邻近二维载气通道的脉冲掺杂层以调整阈值电压。 进一步优选的实施例具有包含未转换的n +的残留层的导电型转换栅极（50），其与脉冲掺杂层阈值移位配合，以产生对n沟道为小且为正的阈值电压，对于p- 通道设备。

公开(公告)号：US5159700A

公开(公告)日：1992-10-27

申请号：US668666

申请日：1991-03-13

申请人： Lee R. Reid, deceased ,  Han-Tzong Yuan

发明人： Lee R. Reid, deceased ,  Han-Tzong Yuan

IPC分类号： G02B6/43 ,  H01L31/12 ,  H04B10/20

CPC分类号： H01L31/12 ,  G02B6/43

摘要： A circuit composed of a circuit board of crystalline elemental silicon slice and circuit components in the form of semiconductor integrated circuits therein which are preferably formed of a Group III-V compound. Signals from each of the integrated circuits are transmitted to other integrated circuits on the board or externally of the board either by conventional printed conductors on the board or by a laser formed in each integrated circuit at each output terminal thereon which transmits light signals along light transmitting members in the silicon board to detectors at the input locations on other ones of the integrated circuits on the board for external to the board. The light signal is transferred from an integrated circuit output to an integrated circuit input or to a device external to the board by means of light transmitting members. These light transmitting members may be light conducting waveguides positioned either on the surface of the board or in grooves formed therein. Alternatively, the light transmitting members can be silicon dioxide paths formed in the silicon circuit board by selective oxidation of the silicon board to form silicon dioxide light transmitting paths therein. Each light transmitting path is coupled between a light emitting output from an integrated circuit and a light receiving input of another integrated circuit on the same or a different semiconductor chip or travels to the edge of the circuit board for transmission external of the board.

摘要翻译： 由晶体元素硅片的电路板和其中半导体集成电路形式的电路元件组成的电路，其优选由III-V族化合物形成。 来自每个集成电路的信号通过板上的常规印刷导体或者在其上的每个集成电路中形成的激光器传输到板上或板外部的其它集成电路，其上的每个输出端子上的激光器沿着透光 硅板中的成员到板上外部的集成电路上的输入位置处的检测器。 光信号通过透光元件从集成电路输出传送到集成电路输入或者传输到板外部的器件。 这些透光构件可以是位于板的表面上或形成在其中的凹槽中的导光波导。 或者，透光构件可以是通过硅板的选择性氧化在硅电路板中形成的二氧化硅路径，以在其中形成二氧化硅光透射路径。 每个光传输路径耦合在相同或不同的半导体芯片上的集成电路的发光输出和另一集成电路的光接收输入之间，或者传播到电路板的边缘以便在板外传输。

公开(公告)号：US6008519A

公开(公告)日：1999-12-28

申请号：US990549

申请日：1997-12-15

申请人： Han-Tzong Yuan ,  Donald L. Plumpton ,  Jau-Yuann Yang ,  Tae S. Kim

发明人： Han-Tzong Yuan ,  Donald L. Plumpton ,  Jau-Yuann Yang ,  Tae S. Kim

IPC分类号： H01L21/335 ,  H01L29/772 ,  H01L29/76 ,  H01L29/74 ,  H01L29/80

CPC分类号： H01L29/66416 ,  H01L29/7722

摘要： A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

摘要翻译： 一种包括第一导电类型的第一半导体层（14）的垂直晶体管（70）。 设置在第一半导体层（14）上的第二导电类型的栅极结构（32）。 栅极结构（32）可以包括由通道（40）分开的多个栅极（38）。 第一导电类型的第二半导体层（50）可以设置在栅极结构（32）上和通道（40）中。 止动元件（36）可以设置在栅极（38）和第二半导体层（50）的上表面之间。 可以在栅极（38）上的第二半导体层（50）中形成空穴（52）。

公开(公告)号：US5548141A

公开(公告)日：1996-08-20

申请号：US441847

申请日：1995-05-16

申请人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

发明人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/161

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  Y10S148/011 ,  Y10S148/072

摘要： A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

摘要翻译： 自发对准发射极接触的方法包括在集电极层（16）的一部分上形成基极层（18）。 界面层（22）形成在基底层（18）上，使得基底层（18）的一部分保持暴露。 发射极层（24）形成在集电层（16），界面层（22）和基层（18）的露出部分上。 在基底层（18）的预先暴露的区域上的发射极层（24）上形成发射极覆盖层（26）。 绝缘层（28）形成在界面层（22）上。 在基底层（18）的预先暴露的区域处，在发射极盖层（26）上形成发射极触点（36）。 绝缘层（28）将发射极触点（36）与基底层（18）和随后形成的基部触点（38）隔离开来。 绝缘层（28）确保发射极触点（36）和基极触点（38）之间的隔离，尽管发射极触点（36）在形成期间未对准。

公开(公告)号：US5420052A

公开(公告)日：1995-05-30

申请号：US230357

申请日：1994-04-19

申请人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

发明人： Francis J. Morris ,  Jau-Yuann Yang ,  Donald L. Plumton ,  Han-Tzong Yuan

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L21/265

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  Y10S148/072

摘要： A method of fabricating a semiplanar heterojunction bipolar transistor (10) includes forming a subcollector layer (12) and a collector layer (16) onto a substrate layer (14). A collector implant plug (18) is selectively implanted to connect the subcollector layer (12) to the surface of the heterojunction bipolar transistor (10). A second epitaxial growth process causes a base layer (22), an emitter layer (24), and an emitter cap layer (26) to form on the collector layer (16) and the collector implant plug (18). By this process, the base layer (22) is not exposed to subsequent harmful fabrication steps. A base plug region (28) is selectively implanted to connect the base layer (22) to the surface of the heterojunction bipolar transistor (10). A base contact (32) and an emitter contact (30) are selectively formed within the heterojunction region on the base plug region (28) and the emitter cap layer (26), respectively. Lateral parasitic diodes between the base contact (32) and the emitter contact (30) are etched away to isolate the base contact (32) from the emitter contact (30). The emitter cap layer (26), the emitter layer (24), and the base layer (22) are removed from the vicinity of the collector implant plug (18) to allow formation of the collector contact (34).

摘要翻译： 制造半平面异质结双极晶体管（10）的方法包括在衬底层（14）上形成子集电极层（12）和集电极层（16）。 选择性地注入集电极注入插头（18）以将子集电极层（12）连接到异质结双极晶体管（10）的表面。 第二外延生长工艺使得在集电极层（16）和集电极植入插头（18）上形成基极层（22），发射极层（24）和发射极盖层（26）。 通过该过程，基层（22）不暴露于随后的有害制造步骤。 选择性地注入基座区域（28）以将基极层（22）连接到异质结双极晶体管（10）的表面。 基极触点（32）和发射极触点（30）分别选择性地形成在基插塞区域（28）和发射极盖层（26）上的异质结区域内。 基极触点（32）和发射极触点（30）之间的侧向寄生二极管被蚀刻掉以将基极触点（32）与发射极触点（30）隔离。 发射极帽层（26），发射极层（24）和基底层（22）从集电极植入插头（18）的附近被去除，以形成集电极触点（34）。

公开(公告)号：US5231037A

公开(公告)日：1993-07-27

申请号：US876252

申请日：1992-04-30

申请人： Han-Tzong Yuan ,  Tae S. Kim ,  Francis J. Morris

发明人： Han-Tzong Yuan ,  Tae S. Kim ,  Francis J. Morris

IPC分类号： H01L29/80 ,  H01L21/335 ,  H01L21/337 ,  H01L29/207 ,  H01L29/772

CPC分类号： H01L29/66454 ,  H01L29/207 ,  H01L29/66924 ,  H01L29/7722 ,  Y10S148/04

摘要： This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.