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公开(公告)号：US20120099243A1
公开(公告)日：2012-04-26
申请号：US13344714
申请日：2012-01-06
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01G4/005
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。
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公开(公告)号：US08138539B2
公开(公告)日：2012-03-20
申请号：US11947591
申请日：2007-11-29
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01L27/108 , H01L21/20
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。
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公开(公告)号：US08569820B2
公开(公告)日：2013-10-29
申请号：US13344714
申请日：2012-01-06
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01L27/108
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。
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公开(公告)号：US20090141424A1
公开(公告)日：2009-06-04
申请号：US11947591
申请日：2007-11-29
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。
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公开(公告)号：US07268383B2
公开(公告)日：2007-09-11
申请号：US10370535
申请日：2003-02-20
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01G4/228 , H01G4/33 , H01L21/76838 , H01L27/0233 , H01L27/1085 , Y10T29/417
摘要： Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.
摘要翻译： 具有由高k电介质形成的电容器和在电介质两侧的一对互连件的半导体器件与制造这种半导体器件的方法一起提供。 互连包括通孔和金属层。
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公开(公告)号：US07615440B2
公开(公告)日：2009-11-10
申请号：US11851969
申请日：2007-09-07
IPC分类号： H01L21/8242
CPC分类号： H01G4/228 , H01G4/33 , H01L21/76838 , H01L27/0233 , H01L27/1085 , Y10T29/417
摘要： In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.
摘要翻译： 在制造半导体器件的方法中，在间隔电介质内形成金属层。 金属层包括通过层间电介质的区域与第二金属线分离的第一金属线。 在第一金属线和第二金属线之间去除层间电介质的区域。 在去除了层间电介质的区域中的第一金属线和第二金属线之间形成高k电介质，使得由第一金属线，第二金属线和高k电介质形成电容器。
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公开(公告)号：US20070294871A1
公开(公告)日：2007-12-27
申请号：US11851969
申请日：2007-09-07
IPC分类号： H01G9/004
CPC分类号： H01G4/228 , H01G4/33 , H01L21/76838 , H01L27/0233 , H01L27/1085 , Y10T29/417
摘要： In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.
摘要翻译： 在制造半导体器件的方法中，在间隔电介质内形成金属层。 金属层包括通过层间电介质的区域与第二金属线分离的第一金属线。 在第一金属线和第二金属线之间去除层间电介质的区域。 在去除了层间电介质的区域中的第一金属线和第二金属线之间形成高k电介质，使得由第一金属线，第二金属线和高k电介质形成电容器。
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公开(公告)号：US20050282346A1
公开(公告)日：2005-12-22
申请号：US11210094
申请日：2005-08-23
IPC分类号： H01L21/02 , H01L21/285 , H01L21/316 , H01L21/318 , H01L27/08 , H01L21/336 , H01L21/20
CPC分类号： H01L28/40 , H01L21/28568 , H01L21/31604 , H01L21/31616 , H01L21/3185 , H01L27/0805 , H01L28/55 , H01L28/75
摘要： A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.
摘要翻译： 一种用于形成MIM电容器的方法和由其形成的MIM电容器器件。 优选实施例包括在包括MIM电容器底板的晶片上选择性地形成第一盖层，以及在MIM电容器底板上沉积绝缘层。 用MIM电容器顶板图案对绝缘层进行构图，并且在图案化绝缘层上沉积MIM电介质材料。 在MIM介电材料上沉积导电材料，并且平坦化晶片以从绝缘层的顶表面去除导电材料和MIM电介质材料，并形成MIM电容器顶板。 在MIM电容器顶板上选择性地形成第二盖层。
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公开(公告)号：US06960835B2
公开(公告)日：2005-11-01
申请号：US10698057
申请日：2003-10-30
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.
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公开(公告)号：US20050093159A1
公开(公告)日：2005-05-05
申请号：US10698057
申请日：2003-10-30
IPC分类号： H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/532 , H01L29/00
CPC分类号： H01L23/5329 , H01L21/76801 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.
摘要翻译： 在半导体集成电路器件中，可以通过在通孔和覆盖在通孔之间的硬电介质层之间引入应力消除层来减小通孔上的热机械应力。
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