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19 条记录 (耗时 0.027 秒)

    Semiconductor nano-wire devices and methods of fabrication
    7.
    发明授权
    Semiconductor nano-wire devices and methods of fabrication 有权
    半导体纳米线器件及其制造方法

    公开(公告)号：US07452778B2

    公开(公告)日：2008-11-18

    申请号：US11104348

    申请日：2005-04-12

    申请人： Hung-Wei Chen ,  Yee-Chia Yeo ,  Di-Hong Lee ,  Fu-Liang Yang ,  Chenming Hu

    发明人： Hung-Wei Chen ,  Yee-Chia Yeo ,  Di-Hong Lee ,  Fu-Liang Yang ,  Chenming Hu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42384 ,  B82Y10/00 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78645 ,  H01L29/78696

    摘要： Nano-wires, preferably of less than 20 nm diameter, can be formed with minimized risk of narrowing and breaking that results from silicon atom migration during an annealing process step. This is accomplished by masking portion of the active layer where silicon atomer would otherwise agglomerate with a material such as silicon dioxide, silicon nitride, or other dielectric that eliminates or substantially reduces the silicon atom migration. Nano-wires, nanotubes, nano-rods, and other features can be formed and can optionally be incorporated into devices, such as by use as a channel region in a transistor device.

    摘要翻译： 可以形成直径小于20nm的纳米线，其最小化是在退火工艺步骤期间硅原子迁移导致的变窄和断裂的风险。 这是通过掩蔽有源层的一部分来实现的，其中硅一方面将以诸如二氧化硅，氮化硅或其它电介质的材料聚集，其消除或基本上减少硅原子迁移。 可以形成纳米线，纳米管，纳米棒和其它特征，并且可以可选地并入器件中，例如用作晶体管器件中的沟道区。

    Method for forming an SOI structure with improved carrier mobility and ESD protection
    8.
    发明授权
    Method for forming an SOI structure with improved carrier mobility and ESD protection 有权
    用于形成具有改进的载流子迁移率和ESD保护的SOI结构的方法

    公开(公告)号：US07538351B2

    公开(公告)日：2009-05-26

    申请号：US11089405

    申请日：2005-03-23

    申请人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

    发明人： Hung-Wei Chen ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Di-Hong Lee

    IPC分类号： H01L29/10

    CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7843 ,  H01L29/7851 ,  H01L29/7854

    摘要： A semiconductor device and method for forming the same including improved electrostatic discharge protection for advanced semiconductor devices, the semiconductor device including providing semiconductor substrate having a pre-selected surface orientation and crystal direction; an insulator layer overlying the semiconductor substrate; a first semiconductor active region overlying the insulator layer having a first surface orientation selected from the group consisting of and ; a second semiconductor active region extending through a thickness portion of the insulator layer having a second surface orientation selected from the group consisting of and different from the first surface orientation; wherein MOS devices including a first MOS device of a first conduction type is disposed on the first semiconductor active region and a second MOS device of a second conduction type is disposed on the second semiconductor active region.

    摘要翻译： 一种半导体器件及其制造方法，包括提供先进半导体器件的改进的静电放电保护，所述半导体器件包括提供具有预选择的表面取向和晶体方向的半导体衬底; 覆盖半导体衬底的绝缘体层; 覆盖绝缘体层的第一半导体有源区具有选自<100>和<110>的第一表面取向; 延伸穿过绝缘体层的厚度部分的第二半导体有源区，其具有选自与第一表面取向不同的<110>和<100>的第二表面取向; 其中包括第一导电类型的第一MOS器件的MOS器件设置在第一半导体有源区上，并且第二导电类型的第二MOS器件设置在第二半导体有源区上。

    Semiconductor device employing an extension spacer and a method of forming the same
    9.
    发明授权
    Semiconductor device employing an extension spacer and a method of forming the same 有权
    采用延伸间隔物的半导体装置及其形成方法

    公开(公告)号：US07265425B2

    公开(公告)日：2007-09-04

    申请号：US10989073

    申请日：2004-11-15

    申请人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

    发明人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

    IPC分类号： H01L29/94

    CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76829 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7843

    摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

    摘要翻译： 形成在半导体衬底上的半导体器件及其形成方法。 在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。 该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。 半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。 源极/漏极延伸在电介质衬垫和延伸垫片下面。 半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。 因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

    FinFET split gate EEPROM structure and method of its fabrication
    10.
    发明授权
    FinFET split gate EEPROM structure and method of its fabrication 有权
    FinFET分裂门EEPROM结构及其制作方法

    公开(公告)号：US07205601B2

    公开(公告)日：2007-04-17

    申请号：US11148903

    申请日：2005-06-09

    申请人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

    发明人： Di-Hong Lee ,  Hsun-Chih Tsao ,  Kuang-Hsin Chen ,  Hung-Wei Chen

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

    摘要： A FinFET split gate EEPROM structure includes a semiconductor substrate and an elongated semiconductor fin extending above the substrate. A control gate straddles the fin, the fin's sides and a first drain-proximate portion of a channel between a source and drain in the fin. The control gate includes a tunnel layer and a floating electrode over which are a first insulative stratum and a first conductive stratum. A select gate straddles the fin and its sides and a second, source-promixate portion of the channel. The select gate includes a second insulative stratum and a second conductive stratum. The insulative strata are portions of a continuous insulative layer covering the substrate and the fin. The conductive strata are electrically continuous portions of a continuous conductive layer formed on the insulative layer.

    摘要翻译： FinFET分离栅极EEPROM结构包括半导体衬底和在衬底上延伸的细长半导体鳍片。 控制栅极横跨鳍片，翅片的侧面以及翅片中的源极和漏极之间的通道的第一漏极 - 近似部分。 控制门包括隧道层和浮动电极，第一绝缘层和第一导电层在其上形成。 选择栅极横跨鳍片及其侧面以及通道的第二个源极扩展部分。 选择门包括第二绝缘层和第二导电层。 绝缘层是覆盖基板和翅片的连续绝缘层的部分。 导电层是形成在绝缘层上的连续导电层的电连续部分。