公开(公告)号：US07265425B2

公开(公告)日：2007-09-04

申请号：US10989073

申请日：2004-11-15

申请人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

发明人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

IPC分类号： H01L29/94

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76829 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

摘要翻译： 形成在半导体衬底上的半导体器件及其形成方法。 在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。 该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。 半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。 源极/漏极延伸在电介质衬垫和延伸垫片下面。 半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。 因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

公开(公告)号：US20060102955A1

公开(公告)日：2006-05-18

申请号：US10989073

申请日：2004-11-15

申请人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

发明人： Kuang-Hsin Chen ,  Tang-Xuan Zhong ,  Chien-Chao Huang ,  Cheng-Kuo Wen ,  Di-Hong Lee

IPC分类号： H01L21/338 ,  H01L31/062

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76829 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device formed on a semiconductor substrate and a method of forming the same. In one embodiment, the semiconductor device includes a gate over the semiconductor substrate and a dielectric liner on a sidewall of the gate. The semiconductor device also includes an extension spacer adjacent and extending laterally beyond the dielectric liner along the semiconductor substrate. The semiconductor device further includes a source/drain located below an upper surface of the semiconductor substrate and adjacent a channel region under the gate. The source/drain extends under the dielectric liner and the extension spacer. The semiconductor device still further includes a silicide region over a portion of the source/drain and extending laterally beyond the extension spacer along the semiconductor substrate. Thus, the extension spacer is interposed between the dielectric liner and the silicide region located over a portion of the source/drain.

摘要翻译： 形成在半导体衬底上的半导体器件及其形成方法。 在一个实施例中，半导体器件包括半导体衬底上的栅极和栅极侧壁上的电介质衬垫。 该半导体器件还包括一个与半导体衬底相邻且沿着绝缘衬垫横向延伸延伸的间隔件。 半导体器件还包括位于半导体衬底的上表面下方并与栅极下方的沟道区相邻的源极/漏极。 源极/漏极延伸在电介质衬垫和延伸垫片下面。 半导体器件还包括在源极/漏极的一部分上方的硅化物区域，并且沿着半导体衬底横向延伸超过延伸间隔物。 因此，延伸间隔物介于电介质衬垫和位于源极/漏极的一部分之上的硅化物区域之间。

公开(公告)号：US07923759B2

公开(公告)日：2011-04-12

申请号：US11400853

申请日：2006-04-10

申请人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

IPC分类号： H01L29/768

CPC分类号： H01L29/66553 ,  H01L21/28097 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

摘要翻译： 一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。 形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。 这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。 然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。 然后金属层与栅电极反应形成金属栅极。

公开(公告)号：US20060202237A1

公开(公告)日：2006-09-14

申请号：US11400853

申请日：2006-04-10

申请人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

IPC分类号： H01L29/768

CPC分类号： H01L29/66553 ,  H01L21/28097 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

摘要翻译： 一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。 形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。 这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。 然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。 然后金属层与栅电极反应形成金属栅极。

公开(公告)号：US20050212015A1

公开(公告)日：2005-09-29

申请号：US10810950

申请日：2004-03-25

申请人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L29/66553 ,  H01L21/28097 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

摘要翻译： 一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。 形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。 这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。 然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。 然后金属层与栅电极反应形成金属栅极。

公开(公告)号：US20080171419A1

公开(公告)日：2008-07-17

申请号：US11652624

申请日：2007-01-12

申请人： Cheng-Kuo Wen ,  Chien-Chao Huang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Hsun-Chih Tsao

发明人： Cheng-Kuo Wen ,  Chien-Chao Huang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Hsun-Chih Tsao

IPC分类号： H01L21/76 ,  H01L21/44

CPC分类号： H01L29/78603 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/785

摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.

摘要翻译： 提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。 该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

公开(公告)号：US07638376B2

公开(公告)日：2009-12-29

申请号：US11652624

申请日：2007-01-12

申请人： Cheng-Kuo Wen ,  Chien-Chao Huang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Hsun-Chih Tsao

发明人： Cheng-Kuo Wen ,  Chien-Chao Huang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Hsun-Chih Tsao

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/78603 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/785

摘要： A method for forming a substrate contact on a silicon-on-insulator (SOI) wafer is provided that can be integrated with a process for fabricating SOI devices without additional processing after wafer dicing. The method is applicable in many of the more advanced packaging technologies, e.g., such as flip chip and die stacking, directly creating a contact to silicon substrate via the front of the diced SOI wafer.

摘要翻译： 提供了一种用于在绝缘体上硅（SOI）晶片上形成衬底接触的方法，其可以与在SOI晶片切割之后不进行额外处理的SOI器件的工艺集成。 该方法可应用于许多较先进的封装技术，例如倒装芯片和芯片堆叠，通过切割的SOI晶片的正面直接产生与硅衬底的接触。

公开(公告)号：US20050230763A1

公开(公告)日：2005-10-20

申请号：US10824854

申请日：2004-04-15

申请人： Chien-Chao Huang ,  Cheng-Kuo Wen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Cheng-Kuo Wen ,  Fu-Liang Yang

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823842 ,  H01L29/41791 ,  H01L29/7833 ,  H01L2029/7858

摘要： A method of manufacturing a microelectronic device. The method includes providing a substrate and forming a patterned feature located over the substrate and a plurality of doped regions. The patterned feature also comprises at least one electrode, wherein the electrode is proximate a plurality of doped layers. The method further includes forming a sill located within the electrode, wherein the sill comprising at least one impurity and adapted for modifying an electrical property of at least one member adjacent the electrode.

摘要翻译： 一种制造微电子器件的方法。 该方法包括提供衬底并形成位于衬底上方的图案化特征以及多个掺杂区域。 图案化特征还包括至少一个电极，其中电极接近多个掺杂层。 所述方法还包括形成位于所述电极内的基台，其中所述基底包括至少一种杂质并且适于改变邻近所述电极的至少一个构件的电性能。

公开(公告)号：US09673280B2

公开(公告)日：2017-06-06

申请号：US11714416

申请日：2007-03-06

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：US08319962B2

公开(公告)日：2012-11-27

申请号：US13398165

申请日：2012-02-16

申请人： Chih-Chiang Tu ,  Chien-Chao Huang

发明人： Chih-Chiang Tu ,  Chien-Chao Huang

IPC分类号： G01N21/00 ,  G06K9/00

CPC分类号： G03F1/84

摘要： The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features.