公开(公告)号：US20080263492A1

公开(公告)日：2008-10-23

申请号：US11833119

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

IPC分类号： G06F17/50

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

摘要翻译： 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

公开(公告)号：US08286114B2

公开(公告)日：2012-10-09

申请号：US11833119

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Sheng-Chen Chung ,  Chih-Tsung Yao ,  Jung-Hui Kao ,  Chung Long Cheng ,  Gary Shen ,  Gwan Sin Chang

IPC分类号： G06F17/50

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.

摘要翻译： 提供了一种用于定义诸如finFET的3-D器件的布局的方法。 该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。 对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。 此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

公开(公告)号：US07632729B2

公开(公告)日：2009-12-15

申请号：US11527616

申请日：2006-09-27

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US20080258228A1

公开(公告)日：2008-10-23

申请号：US11833128

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

公开(公告)号：US20080076215A1

公开(公告)日：2008-03-27

申请号：US11527616

申请日：2006-09-27

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US07898037B2

公开(公告)日：2011-03-01

申请号：US11833128

申请日：2007-08-02

申请人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

发明人： Harry Chuang ,  Kong-Beng Thei ,  Mong Song Liang ,  Jung-Hui Kao ,  Sheng-Chen Chung ,  Chung Long Cheng ,  Shun-Jang Liao

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/76807 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

摘要： A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a contact extending from a top surface of the first ILD into the first ILD; a second ILD over the first ILD; a bottom inter-metal dielectric (IMD) over the second ILD; and a dual damascene structure comprising a metal line in the IMD and a via in the second ILD, wherein the via is connected to the contact.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的第一层间电介质（ILD）; 从第一ILD的顶表面延伸到第一ILD中的接触; 第一个ILD的第二个ILD; 在第二ILD上的底部金属间电介质（IMD）; 以及包括IMD中的金属线和第二ILD中的通孔的双镶嵌结构，其中所述通孔连接到所述触点。

公开(公告)号：US20080003734A1

公开(公告)日：2008-01-03

申请号：US11520377

申请日：2006-09-13

申请人： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

发明人： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/7843

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

摘要翻译： 一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成 在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。 在具有NMOS器件的区域中，相同的应力记忆层没有减小。 在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

公开(公告)号：US07678636B2

公开(公告)日：2010-03-16

申请号：US11520377

申请日：2006-09-13

申请人： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

发明人： Harry Chuang ,  Mong-Song Liang ,  Kong-Beng Thei ,  Jung-Hui Kao ,  Chung Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo

IPC分类号： H01L21/8238 ,  H01L21/337

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/7843

摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate comprising a first region and a second region, forming a first PMOS device in the first region wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration, forming a stress memorization layer over the first PMOS device, reducing the stress memorization layer in the first region, performing an annealing after the step of reducing the stress memorization layer in the first region, and removing the stress memorization layer. The same stress memorization layer is not reduced in a region having an NMOS device. The same stress memorization layer may not be reduced in a region including a second PMOS device.

摘要翻译： 一种形成半导体结构的方法包括提供包括第一区域和第二区域的半导体衬底，在第一区域中形成第一PMOS器件，其中第一PMOS器件的第一栅电极具有第一p型杂质浓度，形成 在第一PMOS器件上方的应力记忆层，减小第一区域中的应力存储层，在减少第一区域中的应力存储层的步骤之后进行退火，以及去除应力存储层。 在具有NMOS器件的区域中，相同的应力记忆层没有减小。 在包括第二PMOS器件的区域中，相同的应力记忆层可能不会减小。

公开(公告)号：US20080315320A1

公开(公告)日：2008-12-25

申请号：US11766425

申请日：2007-06-21

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong Song Liang

IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

公开(公告)号：US20110260251A1

公开(公告)日：2011-10-27

申请号：US13178755

申请日：2011-07-08

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L27/12

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。