公开(公告)号：US08383427B2

公开(公告)日：2013-02-26

申请号：US13566739

申请日：2012-08-03

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

摘要翻译： 提供一种具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由层叠结构形成，其通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜而获得。 下部和上部磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在上磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）作为构成材料的物质，硬掩模含有结晶钽（Ta）作为构成材料的物质。 硬掩模的膜厚大于CAP层的膜厚。

公开(公告)号：US20090302404A1

公开(公告)日：2009-12-10

申请号：US12463865

申请日：2009-05-11

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L29/82 ,  H01L21/28

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having an MTJ device excellent in operating characteristics and a manufacturing method therefor are obtained. The MTJ device is formed of a laminated structure obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower magnetic film and the upper magnetic film contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film of the MTJ device and a hard mask is formed over the CAP layer. The CAP layer contains a simple substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a simple substance of crystalline tantalum (Ta) as a constituent material. The hard mask is so formed that the film thickness thereof is larger than the film thickness of the CAP layer.

摘要翻译： 获得具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜获得的层叠结构形成。 下磁性膜和上磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在MTJ装置的上部磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）的单一物质作为构成材料，硬掩模含有作为构成材料的结晶钽（Ta）的单一物质。 硬掩模被形成为使得其膜厚度大于CAP层的膜厚度。

公开(公告)号：US20070190724A1

公开(公告)日：2007-08-16

申请号：US11690704

申请日：2007-03-23

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

摘要翻译： 本发明的目的是提供一种能够在非易失性存储器的缩放进行时能够在一个存储单元中保持多位信息的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽（TRI）。 然后，使位于沟槽（TR1）的栅极绝缘膜（120）的氮化硅膜（122）中的源极侧部分和漏极侧部分作为能够保持的第一和第二电荷保持部 电荷（CH 1）和（CH 2）。 在电荷（CH 1）被捕获并且电荷（CH 2）然后被捕获的情况下，因此，沟槽（TR 1）中的栅电极（130）的部分（130a）用作 一个盾牌 如果向栅电极（130）施加固定电位，则第二电荷保持部不受电荷（CH 1）引起的电场（EF 1）的影响，使得电荷（CH 2）不被抑制。

公开(公告)号：US07180773B2

公开(公告)日：2007-02-20

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US20060087874A1

公开(公告)日：2006-04-27

申请号：US11253696

申请日：2005-10-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C5/06

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W 1和T 1，数字线的厚度表示为T 2，并且从数字线的中心到厚度方向的中心的距离 在厚度方向上的MTJ元件的自由层表示为L 1。 数字线的宽度表示为W 2，并且从厚度方向的位线的中心到厚度方向上的MTJ元件的自由层的中心的距离表示为L 2。 距离L 1和L 2以及横截面积S 1和S 2被设定为当L 1 / L 2> = 1时，关于（1/3）（L 1 / L 2 ）满足<= S 2 / S 1 <= 1，并且当L 1 / L 2 <= 1时，满足1 <= S 2 / S 1 <= 3（L 1 / L 2）的关系。

公开(公告)号：US20120301975A1

公开(公告)日：2012-11-29

申请号：US13566739

申请日：2012-08-03

申请人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

发明人： Ryoji Matsuda ,  Shuichi Ueno ,  Haruo Furuta ,  Takashi Takenaga ,  Takeharu Kuroiwa

IPC分类号： H01L21/02

CPC分类号： H01L43/08 ,  H01L27/228 ,  H01L43/12

摘要： A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.

摘要翻译： 提供一种具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由层叠结构形成，其通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜而获得。 下部和上部磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。 隧道绝缘膜包含氧化铝（AlOx）作为构成材料。 在上磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）作为构成材料的物质，硬掩模含有结晶钽（Ta）作为构成材料的物质。 硬掩模的膜厚大于CAP层的膜厚。

公开(公告)号：US20090315128A1

公开(公告)日：2009-12-24

申请号：US12549695

申请日：2009-08-28

申请人： Haruo Furuta ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

发明人： Haruo Furuta ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

IPC分类号： H01L43/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/12

摘要： The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

摘要翻译： 具有包含记忆精度不劣化的TMR膜的存储单元的半导体装置及其制造方法。 在数字线的形成区域的一部分的TMR下电极的平面图中对应的区域选择性地形成TMR元件（TMR膜，TMR上电极）。 TMR上电极由Ta的30-100nm厚度形成，并且在制造过程中也用作硬掩模。 在TMR元件的整个表面和TMR下电极的整个表面上形成由LT-SiN形成的层间绝缘膜，覆盖包括TMR下电极的侧表面的整个表面的层间绝缘膜和 包括LT-SiN。 形成覆盖整个表面并包含SiO 2的层间绝缘膜。

公开(公告)号：US07554837B2

公开(公告)日：2009-06-30

申请号：US12213505

申请日：2008-06-20

申请人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

发明人： Yoshinori Okumura ,  Shuichi Ueno ,  Haruo Furuta

IPC分类号： G11C11/14 ,  G11C11/10

CPC分类号： H01L43/08 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/228

摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.

摘要翻译： 位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离 的厚度方向上的MTJ元件表示为L1。 数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。 距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

公开(公告)号：US20070108543A1

公开(公告)日：2007-05-17

申请号：US11593548

申请日：2006-11-07

申请人： Haruo Furuta ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

发明人： Haruo Furuta ,  Ryoji Matsuda ,  Shuichi Ueno ,  Takeharu Kuroiwa

IPC分类号： H01L43/00

CPC分类号： H01L43/08 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/12

摘要： The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.

摘要翻译： 具有包含记忆精度不劣化的TMR膜的存储单元的半导体装置及其制造方法。 在数字线的形成区域的一部分的TMR下电极的平面图中对应的区域选择性地形成TMR元件（TMR膜，TMR上电极）。 TMR上电极由Ta的30-100nm厚度形成，并且在制造过程中也用作硬掩模。 在TMR元件的整个表面和TMR下电极的整个表面上形成由LT-SiN形成的层间绝缘膜，覆盖包括TMR下电极的侧表面的整个表面的层间绝缘膜和 包括LT-SiN。 形成覆盖整个表面并包括SiO 2的层间绝缘膜。

公开(公告)号：US4485413A

公开(公告)日：1984-11-27

申请号：US303558

申请日：1981-09-23

申请人： Haruo Furuta ,  Toshiji Fujita ,  Chihiko Yamada ,  Masaki Nojima

发明人： Haruo Furuta ,  Toshiji Fujita ,  Chihiko Yamada ,  Masaki Nojima

IPC分类号： G03F3/08 ,  H04N1/00 ,  H04N1/50 ,  H04N1/64 ,  H04N9/495

CPC分类号： H04N1/00294 ,  H04N1/508 ,  H04N1/646 ,  H04N1/00291

摘要： A color television video signal is directly read out in synchronism to the scanning speed of a scanner, the video signal thus read out is converted into three primary color signals, and these three primary color signals are in turn converted into process video signals, which are supplied to the scanner. A printing plate can be produced directly from a television video signal without requiring any color picture original.

摘要翻译： 与扫描仪的扫描速度同步地直接读出彩色电视视频信号，由此读出的视频信号被转换为三原色信号，这三个原色信号又被转换为处理视频信号， 提供给扫描仪。 可以直接从电视视频信号产生印版，而不需要原始的彩色图像。