公开(公告)号：US20050169050A1

公开(公告)日：2005-08-04

申请号：US11052142

申请日：2005-02-08

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TR1) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

摘要翻译： 本发明的目的是提供一种能够在非易失性存储器的缩放进行时能够在一个存储单元中保持多位信息的半导体器件，以及半导体器件的制造方法。 沟槽（TR 1）形成在MONOS晶体管的沟道部分中。 然后，使位于沟槽（TR1）的栅极绝缘膜（120）的氮化硅膜（122）中的源极侧部分和漏极侧部分作为能够保持的第一和第二电荷保持部 电荷（CH 1）和（CH 2）。 在电荷（CH 1）被捕获并且电荷（CH 2）然后被捕获的情况下，因此，沟槽（TR 1）中的栅电极（130）的部分（130a）用作 一个盾牌 如果向栅电极（130）施加固定电位，则第二电荷保持部不受电荷（CH 1）引起的电场（EF 1）的影响，使得电荷（CH 2）不被抑制。

公开(公告)号：US06417555B1

公开(公告)日：2002-07-09

申请号：US09225469

申请日：1999-01-06

申请人： Shuuichi Ueno ,  Yasuo Inoue ,  Masayoshi Shirahata

发明人： Shuuichi Ueno ,  Yasuo Inoue ,  Masayoshi Shirahata

IPC分类号： H01L2900

CPC分类号： H01L21/76224

摘要： A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilcon film.

摘要翻译： 具有高绝缘特性的沟槽隔离结构的半导体器件以及半导体器件的制造方法适用于半导体器件的小型化，防止漏电流。 在要形成沟槽隔离结构的沟槽内的区域中，在半导体衬底和CVD氧化硅膜之间形成小密度多晶硅膜。 通过改变聚硅氧烷膜的晶体结构，可以减轻在热处理期间在半导体衬底和CVD氧化硅膜之间产生的机械应力。

公开(公告)号：US20070190724A1

公开(公告)日：2007-08-16

申请号：US11690704

申请日：2007-03-23

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

摘要翻译： 本发明的目的是提供一种能够在非易失性存储器的缩放进行时能够在一个存储单元中保持多位信息的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽（TRI）。 然后，使位于沟槽（TR1）的栅极绝缘膜（120）的氮化硅膜（122）中的源极侧部分和漏极侧部分作为能够保持的第一和第二电荷保持部 电荷（CH 1）和（CH 2）。 在电荷（CH 1）被捕获并且电荷（CH 2）然后被捕获的情况下，因此，沟槽（TR 1）中的栅电极（130）的部分（130a）用作 一个盾牌 如果向栅电极（130）施加固定电位，则第二电荷保持部不受电荷（CH 1）引起的电场（EF 1）的影响，使得电荷（CH 2）不被抑制。

公开(公告)号：US06737336B2

公开(公告)日：2004-05-18

申请号：US10183408

申请日：2002-06-28

申请人： Shuuichi Ueno ,  Yasuo Inoue ,  Masayoshi Shirahata

发明人： Shuuichi Ueno ,  Yasuo Inoue ,  Masayoshi Shirahata

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A semiconductor device having a trench isolation structure which has a high insulating characteristic, is suitable for miniaturizing a semiconductor device, and prevents a leakage current, as well as a method of manufacturing the semiconductor device. A small-density polysilicon film is formed between a semiconductor substrate and a CVD silicon oxide film in the area within a trench where a trench isolation structure is to be formed. Mechanical stress that develops between the semiconductor substrate and the CVD silicon oxide film during heat treatment is mitigated by changing the crystalline structure of the polysilicon film.

摘要翻译： 具有高绝缘特性的沟槽隔离结构的半导体器件以及半导体器件的制造方法适用于半导体器件的小型化，防止漏电流。 在要形成沟槽隔离结构的沟槽内的区域中，在半导体衬底和CVD氧化硅膜之间形成小密度多晶硅膜。 通过改变多晶硅膜的结晶结构来减轻在热处理期间在半导体衬底和CVD氧化硅膜之间产生的机械应力。

公开(公告)号：US06503799B2

公开(公告)日：2003-01-07

申请号：US09991959

申请日：2001-11-26

申请人： Katsuyuki Horita ,  Takashi Kuroi ,  Shuuichi Ueno

发明人： Katsuyuki Horita ,  Takashi Kuroi ,  Shuuichi Ueno

IPC分类号： H01L21205

CPC分类号： H01L21/76264 ,  H01L21/76272

摘要： There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.

公开(公告)号：US06867455B2

公开(公告)日：2005-03-15

申请号：US10600344

申请日：2003-06-23

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： A semiconductor device capable of holding multibit information in one memory cell, and a method of manufacturing the semiconductor device. A trench is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film of a gate insulating film which interpose the trench are caused to function as first and second electric charge holding portions capable of holding electric charges. In the case in which first electric charges are trapped on the drain side and second electric charges are trapped on the source side, a portion of a gate electrode in the trench functions as a shield. If a fixed potential is given to the gate electrode, the second electric charge holding portion is not influenced by an electric field induced by the first electric charges so that the trapping of the second electric charges is not inhibited.

摘要翻译： 一种能够将多位信息保持在一个存储单元中的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽。 然后，使介入沟槽的栅极绝缘膜的氮化硅膜中的源极侧部分和漏极侧部分作为能够保持电荷的第一和第二电荷保持部分起作用。 在第一电荷被捕获在漏极侧并且第二电荷被捕获在源极侧的情况下，沟槽中的栅电极的一部分用作屏蔽。 如果向栅电极施加固定电位，则第二电荷保持部不受第一电荷引起的电场的影响，从而不抑制第二电荷的捕获。

公开(公告)号：US06734523B2

公开(公告)日：2004-05-11

申请号：US09395184

申请日：1999-09-14

申请人： Shuuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda

发明人： Shuuichi Ueno ,  Tomohiro Yamashita ,  Hidekazu Oda

IPC分类号： H01L2900

CPC分类号： H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  Y10S257/903

摘要： A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.

摘要翻译： 一种半导体器件，其包括通过沟槽被细分为多个部分，以实现布局面积的减小及其制造方法。 在半导体器件中，元件隔离膜形成为具有从半导体衬底的主表面的深度，并且从衬底的主表面到深度的区域被分成多个第一区域。 在每个第一区域中形成第一孔。 第二阱形成在比衬底中的第一阱更深的第二区域中，并且第二阱与一些第一阱接触。

公开(公告)号：US06498077B2

公开(公告)日：2002-12-24

申请号：US09816519

申请日：2001-03-26

申请人： Shuuichi Ueno ,  Katsuyuki Horita ,  Takashi Kuroi

发明人： Shuuichi Ueno ,  Katsuyuki Horita ,  Takashi Kuroi

IPC分类号： H01L21425

CPC分类号： H01L29/1083 ,  H01L21/26586 ,  H01L27/10808 ,  H01L27/10829 ,  H01L27/10841 ,  H01L27/10873 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/7836

摘要： Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×1018 to 1×1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.

摘要翻译： 本发明提供一种半导体器件及其制造方法，该半导体器件具有能够获得特别是耐穿孔和漏电流降低的保证的良好特性的结构的MOS晶体管。 也就是说，除了通常的MOS晶体管结构之外，通道掺杂区域（1）以预定深度设置，以便在包括沟道区域的P阱区域（22）中的基本上平坦表面的整个表面上延伸。 在通道掺杂区域（1）中，将P型杂质浓度（P的最大值）的最大值设定为1×1018〜1×1019，N型杂质浓度的最大值（N的最大值）为 源极/漏极区域（31（32））不小于10％且不大于100％。 注意，P阱区域（22）的表面邻近区域将超出对象。