摘要:
This invention relates to a method for eliminating or lessening the incidence of boar odor in meat reared from male pigs which comprises administering to such male pigs an effective amount of a boar 4-ene-5-.alpha.-reductase inhibiting compound with or without further active ingredients. Also provided is a method for preventing the formation of 5-.alpha.-androst-16-en-3-one in male pigs which comprises administering to such male pigs a presently discovered boar 4-ene-5-.alpha.-reductase inhibiting compound.
摘要:
A stabilized somatotropin peptide aldehyde complex which provides prolonged release of the somatotropin and enhanced feed efficiency. The complex is prepared by dissolving the somatotropin and peptide aldehyde in water, isolating the complex from the aqueous solution, and crystalizing the product from alcohol. Specifically, the complex comprises porcine somatotropin and leupeptin and is particularly useful for enhancing feed efficiency in swine.
摘要:
A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exists. In response to determining that the pending write operation to the given register exists, the method includes blocking the write operation to the given register from being scheduled. However, in response to determining that the pending write operation to the given register does not exist, the method includes allowing the write operation to the given register to be scheduled. Further, if the pending write operation to the given register does not exist, the method includes allowing a subsequent write operation to a different register within the non-renamed register space to be scheduled.
摘要:
A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the processing mode. The processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state).
摘要:
A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations. A read of the special register may then be performed in order to determine whether a state change is indicated.
摘要:
An automotive fluid control system with pressure balanced solenoid valve [24] and fluid mixing housing [22] is disclosed. The solenoid valve [24] is preferably used in an EGR (exhaust gas circulation) fluid control system, although the valve may be used in other vehicle fluid control systems, such as an engine block cooling liquid control system. A poppet member [84] of an EGR valve is pressured balanced such that only a light spring [170] and armature [88] are needed to control the positioning of the poppet member [84]. Magnetic and inductance sensors [184, 282] are used to accurately determine the position of the poppet member. The fluid mixing housing [22] homogeneously mixes first and second fluids. A portion of a main first fluid flow is funneled off and mixed in the housing [22] with a second fluid prior to being returned to the main fluid flow. Ideally, the housing [22] has a circumferentially extending channel [95] for intercepting, funnelling and mixing the captured portion of the main first fluid flow with the second fluid flow. Also, a solenoid subassembly [82] is disclosed which can mate with a variety of different valve housings [22] and which is adapted to mount on various engine configurations.
摘要:
Use as herbicides of, and herbicidal compositions containing as active ingredients, compounds of the formula: ##STR1## wherein the symbols have assigned meanings.
摘要:
In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.
摘要:
In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.