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    Method of reading data in non-volatile memory device, and device thereof
    1.
    发明授权
    Method of reading data in non-volatile memory device, and device thereof 失效
    在非易失性存储装置中读取数据的方法及其装置

    公开(公告)号：US08547752B2

    公开(公告)日：2013-10-01

    申请号：US13198750

    申请日：2011-08-05

    申请人： Hee Seok Eun ,  Jae Hong Kim ,  Kyoung Lae Cho

    发明人： Hee Seok Eun ,  Jae Hong Kim ,  Kyoung Lae Cho

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5628 ,  G11C16/26 ,  G11C16/3418

    摘要： A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination.

    摘要翻译： 一种在非易失性存储器件中读取数据的方法。 该方法包括使用第一读取级别读取存储单元阵列中的第一页的多个存储单元，使用第二读取级别读取与第一页的存储单元相邻的第二页的多个存储单元，确定 基于第一读取电平来改变第一页面的每个存储器单元的状态，以基于第二读取电平来验证第二页的每个存储单元的阈值电压，并且修改第二页的每个存储器单元的状态 第二页根据确定的结果。

    METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE, AND DEVICE THEREOF
    2.
    发明申请
    METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE, AND DEVICE THEREOF 失效
    在非易失性存储器件中读取数据的方法及其装置

    公开(公告)号：US20120033502A1

    公开(公告)日：2012-02-09

    申请号：US13198750

    申请日：2011-08-05

    申请人： Hee Seok EUN ,  Jae Hong Kim ,  Kyoung Lae Cho

    发明人： Hee Seok EUN ,  Jae Hong Kim ,  Kyoung Lae Cho

    IPC分类号： G11C16/26 ,  G11C16/06

    CPC分类号： G11C11/5628 ,  G11C16/26 ,  G11C16/3418

    摘要： A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination.

    摘要翻译： 一种在非易失性存储器件中读取数据的方法。 该方法包括使用第一读取级别读取存储单元阵列中的第一页的多个存储单元，使用第二读取级别读取与第一页的存储单元相邻的第二页的多个存储单元，确定 基于第一读取电平来改变第一页面的每个存储器单元的状态，以基于第二读取电平来验证第二页的每个存储单元的阈值电压，并且修改第二页的每个存储器单元的状态 第二页根据确定的结果。

    Memory device and memory data determination method
    5.
    发明授权
    Memory device and memory data determination method 有权
    存储器和存储器数据确定方法

    公开(公告)号：US07911848B2

    公开(公告)日：2011-03-22

    申请号：US12461060

    申请日：2009-07-30

    申请人： Heeseok Eun ,  Jae Hong Kim ,  Kyoung Lae Cho

    发明人： Heeseok Eun ,  Jae Hong Kim ,  Kyoung Lae Cho

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5642 ,  G11C16/3418 ,  G11C16/3427

    摘要： A memory device and a memory data determination method are provided. The memory device may estimate a threshold voltage shift of a first memory cell based on data before the first memory cell is programmed and a target program threshold voltage of the first memory cell. The memory device may generate a metric of a threshold voltage shift of a second memory cell based on the estimated threshold voltage shift of the first memory cell. Also, the memory device may determine data stored in the second memory cell based on the metric.

    摘要翻译： 提供存储器件和存储器数据确定方法。 存储器件可以基于第一存储器单元被编程之前的数据和第一存储器单元的目标程序阈值电压来估计第一存储器单元的阈值电压偏移。 存储器件可以基于第一存储器单元的估计的阈值电压偏移来产生第二存储器单元的阈值电压偏移的度量。 此外，存储器设备可以基于度量来确定存储在第二存储器单元中的数据。

    Memory device and data reading method
    6.
    发明授权
    Memory device and data reading method 有权
    存储器和数据读取方式

    公开(公告)号：US07843727B2

    公开(公告)日：2010-11-30

    申请号：US12232138

    申请日：2008-09-11

    申请人： Kyoung Lae Cho ,  Donghun Yu ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim ,  Heeseok Eun

    发明人： Kyoung Lae Cho ,  Donghun Yu ,  Yoon Dong Park ,  Jun Jin Kong ,  Jae Hong Kim ,  Heeseok Eun

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/3418 ,  G11C29/00

    摘要： A memory device and a memory data reading method are provided. The memory device may include: a multi-bit cell array; a programming unit that stores N data pages in a memory page in the multi-bit cell array; and a control unit that divides the N data pages into a first group and second group, reads data of the first group from the memory page, and determines a scheme of reading data of the second group from the memory page based on the read data of the first group.

    摘要翻译： 提供存储器件和存储器数据读取方法。 存储器件可以包括：多位单元阵列; 编程单元，其将N个数据页存储在多位单元阵列中的存储器页面中; 以及控制单元，其将N个数据页划分为第一组和第二组，从存储器页面读取第一组的数据，并且基于读取的数据确定从存储器页面读取第二组的数据的方案 第一组。

    Memory device and memory programming method
    7.
    发明申请
    Memory device and memory programming method 有权
    存储器和存储器编程方法

    公开(公告)号：US20090296486A1

    公开(公告)日：2009-12-03

    申请号：US12382351

    申请日：2009-03-13

    申请人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

    发明人： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

    摘要： Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

    摘要翻译： 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

    Apparatus for determining number of bits to be stored in memory cell
    8.
    发明申请
    Apparatus for determining number of bits to be stored in memory cell 失效
    用于确定要存储在存储单元中的位数的装置

    公开(公告)号：US20090222701A1

    公开(公告)日：2009-09-03

    申请号：US12219103

    申请日：2008-07-16

    申请人： Seung-Hwan Song ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Jae Hong Kim

    发明人： Seung-Hwan Song ,  Kyoung Lae Cho ,  Jun Jin Kong ,  Jae Hong Kim

    IPC分类号： G06F11/00 ,  G06F12/16

    CPC分类号： G11C11/56 ,  G06F11/1012 ,  G11C29/00

    摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.

    摘要翻译： 示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。 根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

    Memory device and error control codes decoding method
    9.
    发明申请
    Memory device and error control codes decoding method 有权
    存储器件和错误控制代码解码方法

    公开(公告)号：US20090177931A1

    公开(公告)日：2009-07-09

    申请号：US12153121

    申请日：2008-05-14

    申请人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Sung Chung Park

    发明人： Seung-Hwan Song ,  Jun Jin Kong ,  Jae Hong Kim ,  Kyoung Lae Cho ,  Sung Chung Park

    IPC分类号： G06F11/07 ,  G06F11/00

    CPC分类号： G06F11/141 ,  G06F11/1012 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/10 ,  G11C29/00

    摘要： Memory devices and/or error control codes (ECC) decoding methods may be provided. A memory device may include a memory cell array, and a decoder to perform hard decision decoding of first data read from the memory cell array by a first read scheme, and to generate output data and error information of the output data. The memory device may also include and a control unit to determine an error rate of the output data based on the error information, and to determine whether to transmit an additional read command for soft decision decoding to the memory cell array based on the error rate. An ECC decoding time may be reduced through such a memory device.

    摘要翻译： 可以提供存储器件和/或错误控制代码（ECC）解码方法。 存储器件可以包括存储单元阵列和解码器，以通过第一读取方案对从存储器单元阵列读取的第一数据进行硬判决解码，并且生成输出数据和输出数据的输出数据和错误信息。 存储器装置还可以包括和控制单元，用于基于错误信息确定输出数据的错误率，并且基于错误率来确定是否向存储器单元阵列发送用于软判决解码的附加读命令。 可以通过这样的存储器件来减少ECC解码时间。