公开(公告)号：US06090304A

公开(公告)日：2000-07-18

申请号：US919659

申请日：1997-08-28

申请人： Helen H. Zhu ,  George A. Mueller ,  Thomas D. Nguyen ,  Lumin Li

发明人： Helen H. Zhu ,  George A. Mueller ,  Thomas D. Nguyen ,  Lumin Li

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  C03C15/00

CPC分类号： H01L21/31116

摘要： Disclosed is a method for improving the selectivity of dielectric layers to photoresist layers and base layers. The method is performed in a plasma processing chamber, and the photoresist layer is coated over the dielectric layer. The method includes introducing an etchant source gas into the plasma processing chamber, which consists essentially of a CxFy gas and an N.sub.2 gas. The method further includes striking a plasma in the plasma processing chamber from the etchant source gas. The method additionally includes etching at least a portion of the dielectric layer with the plasma through to a base layer that underlies the dielectric layer. The method is also well suited for anisotropically etching an oxide layer with very high selectivities to Si, Si.sub.3 N.sub.4, TiN, and metal silicides.

摘要翻译： 公开了一种提高介电层对光致抗蚀剂层和基层的选择性的方法。 该方法在等离子体处理室中进行，光致抗蚀剂层涂覆在电介质层上。 该方法包括将蚀刻剂源气体引入等离子体处理室中，其主要由C x F y气体和N 2气体组成。 该方法还包括从蚀刻剂源气体中冲击等离子体处理室中的等离子体。 该方法还包括用等离子体将介电层的至少一部分蚀刻到在电介质层下面的基底层。 该方法也非常适用于对Si，Si 3 N 4，TiN和金属硅化物具有非常高的选择性的各向异性蚀刻氧化物层。

公开(公告)号：US06410451B1

公开(公告)日：2002-06-25

申请号：US09405949

申请日：1999-09-27

申请人： Thomas D. Nguyen ,  George Mueller ,  Peter McGrath

发明人： Thomas D. Nguyen ,  George Mueller ,  Peter McGrath

IPC分类号： H01L21302

摘要： Improved methods and apparatus for chemically assisted etch processing in a plasma processing system are disclosed. In accordance with one aspect of the invention, improved techniques suitable for performing an etch process in the plasma processing can be realized. The invention operates to reduce the critical dimension bias that is associated with the etch process. Lower critical dimension bias provides many benefits. One such benefit is that features with higher aspect ratio can be etched correctly. In addition, several other undesired effects, e.g., micro loading, bowing and passivation, can be curtailed using the techniques of the present invention.

公开(公告)号：US6117786A

公开(公告)日：2000-09-12

申请号：US71960

申请日：1998-05-05

申请人： Keyvan Khajehnouri ,  Thomas D. Nguyen ,  George Mueller

发明人： Keyvan Khajehnouri ,  Thomas D. Nguyen ,  George Mueller

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/311 ,  H01L21/768 ,  C03C15/00 ,  C03C25/00 ,  H01B13/00

CPC分类号： H01L21/31116 ,  H01L21/76816

摘要： A semiconductor manufacturing process wherein deep and narrow 0.6 micron and smaller openings are plasma etched in doped and undoped silicon oxide. The etching gas includes fluorocarbon, oxygen and nitrogen reactants which cooperate to etch the silicon oxide while providing enough polymer build-up to obtain anisotropically etched openings and avoid etch stop of etched openings having aspect ratios of 5:1 and higher. The process is useful for etching 0.25 micron and smaller contact or via openings and can be carried out in a parallel plate plasma reactor having a showerhead electrode.

摘要翻译： 在掺杂和未掺杂的氧化硅中等离子体蚀刻深度和窄的0.6微米和更小的开口的半导体制造工艺。 蚀刻气体包括碳氟化合物，氧和氮反应物，它们协同蚀刻氧化硅，同时提供足够的聚合物积聚物以获得各向异性蚀刻的开口，并避免蚀刻开始的纵横比为5:1或更高的蚀刻开口。 该方法对于蚀刻0.25微米和更小的接触或通孔开口是有用的，并且可以在具有喷头电极的平行板等离子体反应器中进行。

公开(公告)号：US06733594B2

公开(公告)日：2004-05-11

申请号：US09747703

申请日：2000-12-21

申请人： Thomas D. Nguyen

发明人： Thomas D. Nguyen

IPC分类号： B08B300

CPC分类号： H01L21/67046 ,  Y10S134/902 ,  Y10S438/906 ,  Y10S438/928

摘要： A method and system for processing a wafer is disclosed. The method includes receiving a wafer having a process side and a backside. The method further includes removing un-wanted particles from the backside of the wafer to prevent gaps from forming between the backside of the wafer and a chucking surface. The method also includes performing a specific processing task on the process side of the wafer after cleaning the backside of the wafer.

摘要翻译： 公开了一种用于处理晶片的方法和系统。 该方法包括接收具有处理侧和背面的晶片。 该方法还包括从晶片的背面去除不需要的颗粒，以防止在晶片的背面和卡盘表面之间形成间隙。 该方法还包括在清洁晶片的背面之后在晶片的处理侧执行特定的处理任务。

公开(公告)号：US06217786B1

公开(公告)日：2001-04-17

申请号：US09223963

申请日：1998-12-31

申请人： Graham Hills ,  Thomas D. Nguyen ,  Douglas Keil ,  Keyvan Khajehnouri

发明人： Graham Hills ,  Thomas D. Nguyen ,  Douglas Keil ,  Keyvan Khajehnouri

IPC分类号： B44C122

CPC分类号： H01L21/31116

摘要： A method of etching an oxide layer in a plasma etching reactor is disclosed. The method includes the steps of providing a semiconductor substrate including the oxide layer into the plasma etching reactor and flowing an etching gas that includes a fluorocarbon gas, a nitrogen reactant gas, an oxygen reactant gas, an inert carrier gas, and a hydrogen-containing additive gas into the plasma etching reactor. The method further includes etching an opening at least partially through the oxide layer using a plasma that is formed from the etching gas.

摘要翻译： 公开了蚀刻等离子体蚀刻反应器中的氧化物层的方法。 该方法包括以下步骤：将包括氧化物层的半导体衬底提供到等离子体蚀刻反应器中并使包含碳氟化合物气体，氮气反应气体，氧气反应物气体，惰性载气和含氢气体的蚀刻气体流动 添加气体进入等离子体蚀刻反应器。 该方法还包括使用由蚀刻气体形成的等离子体至少部分地蚀刻通过氧化物层的开口。

公开(公告)号：US06899109B1

公开(公告)日：2005-05-31

申请号：US10802647

申请日：2004-03-16

申请人： Thomas D. Nguyen

发明人： Thomas D. Nguyen

IPC分类号： H01L21/00 ,  B08B3/00

CPC分类号： H01L21/67046 ,  Y10S134/902 ,  Y10S438/906 ,  Y10S438/928

摘要： A system for processing a wafer includes a cleaning module configured to only clean the back side of the wafer so as to remove unwanted particles therefrom before performing subsequent processing tasks on the process side of the wafer. The system also includes a processing module configured to perform processing tasks on the process side of the wafer. The processing module includes a chuck for supporting the wafer during the processing task. The system further includes a transport module configured to remove the cleaned wafer from the cleaning module, move it to the processing module and place it on the chuck of the processing module without performing any intervening manipulations during the movement.

摘要翻译： 一种用于处理晶片的系统包括清洁模块，该清洁模块被配置为仅在晶片的工艺侧执行后续处理任务之前仅清洁晶片的背面，以便从其中去除不需要的颗粒。 该系统还包括处理模块，该处理模块被配置为在晶片的处理侧执行处理任务。 处理模块包括用于在处理任务期间支撑晶片的卡盘。 该系统还包括传送模块，该传送模块被配置为将清洁的晶片从清洁模块移除，将其移动到处理模块并将其放置在处理模块的卡盘上，而不会在运动期间执行任何中间操作。