公开(公告)号：US06798296B2

公开(公告)日：2004-09-28

申请号：US10292225

申请日：2002-11-12

申请人： Heng-Chih Lin ,  Baher S. Haroun ,  Tiang Tun Foo

发明人： Heng-Chih Lin ,  Baher S. Haroun ,  Tiang Tun Foo

IPC分类号： H03L700

CPC分类号： H03K3/0322 ,  H03K5/1252 ,  H03L7/089 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/50

摘要： A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

摘要翻译： 宽带，宽工作范围，通用数字锁相环（PLL）在数字域内运行，除了相关的时间数字转换器（T2D）和数字控制振荡器（DCO）外。 通过快速校准T2D和DCO，无论输入时钟频率，电源电压，处理和温度如何，通过使用校准的相位频率检测（PFD）和DCO信息来对控制回路校正进行归一化来实现恒定的PLL环路BW 变化。 PLL环路BW与操作条件和半导体器件变化完全解耦。 这意味着可以非常积极地选择PLL环路BW来抑制噪声，从而实现低抖动，高性能的PLL。 此外，由于该PLL可以在宽的工作范围内可靠地工作，所以它是一个单一设计的通用PLL。

公开(公告)号：US06784755B2

公开(公告)日：2004-08-31

申请号：US10292276

申请日：2002-11-12

申请人： Heng-Chih Lin ,  Baher S. Haroun

发明人： Heng-Chih Lin ,  Baher S. Haroun

IPC分类号： H03B100

CPC分类号： H03L7/0995 ,  H03K3/0322

摘要： A high PSRR, low power semiconductor digitally controlled oscillator (DCO) architecture employs only one simple current steering D/A converter directly on top of a multi-stage current controlled oscillator. The architecture provides a good building block for many circuit applications, e.g., all digital phase lock loops, direct modulation transmitters for wireless devices, and the like.

摘要翻译： 高PSRR低功耗半导体数字控制振荡器（DCO）架构直接在多级电流控制振荡器的顶部仅使用一个简单的电流导引D / A转换器。 该架构为许多电路应用提供了良好的构建块，例如所有数字锁相环，用于无线设备的直接调制发射机等。

公开(公告)号：US06784699B2

公开(公告)日：2004-08-31

申请号：US10292243

申请日：2002-11-12

申请人： Baher S. Haroun ,  Heng-Chih Lin ,  Tim Foo

发明人： Baher S. Haroun ,  Heng-Chih Lin ,  Tim Foo

IPC分类号： H03K1700

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03K5/1252 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/50

摘要： A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa. More importantly, the complete switch over only takes two cycles of the targeted clock in the best case once the active clock is turned off, when switching from slow to fast clock; and four target clock cycles in the worst case once the active clock is turned off, when switching from fast to slow clock.

摘要翻译： 假设相应的时钟本身是稳定的，对称无毛刺时钟多路复用电路允许在操作期间的任何时刻将数字或模拟处理单元的输入时钟从一个频率切换到另一个频率。 时钟或开关控制信号不以任何方式同步的限制。 该电路保证无毛刺输出，并且还可以防止输出时钟的短暂循环。 由于所有相关时钟和开关控制信号都是异步的，因此该电路进一步消除了元稳定性问题。 其对称架构允许电路工作，输出时钟从慢时钟切换到快时钟，反之亦然。 更重要的是，一旦活动时钟关闭，当从慢速切换到快速时钟时，完全切换只需要两个周期的目标时钟; 在最坏情况下，一旦活动时钟关闭，当从快速切换到慢时钟时，则有四个目标时钟周期。

公开(公告)号：US06614379B2

公开(公告)日：2003-09-02

申请号：US10027710

申请日：2001-12-20

申请人： Heng-Chih Lin ,  Baher S. Haroun

发明人： Heng-Chih Lin ,  Baher S. Haroun

IPC分类号： H03M112

CPC分类号： H03M1/205 ,  H03M1/0682 ,  H03M1/365

摘要： A flash analog-to-digital converter having precise differential voltage interpolation without the use of silicide-blocked resistors. A reference conversion voltage output portion converts an analog input voltage on the basis of a plurality of reference voltages into a plurality of reference conversion voltages. An intermediate voltage generating portion includes a predetermined number of non-linear resistance units respectively provided between one voltage and the other voltage in pairs of a predetermined number of the plurality of reference conversion voltages to generate a plurality of intermediate voltages by resistance division using the predetermined number of non-linear resistance units. In addition, the intermediate voltage generating portion generates a plurality of conversion voltages. A digital data output portion outputs the digital output voltage on the basis of the plurality of conversion voltages using double interpolation. Each of the predetermined number of non-linear resistance units includes a first input terminal connected to the one voltage, a second input terminal connected to the other voltage, and a plurality of non-linear resistor elements having the same resistance value connected in series between the first and second input terminals. The plurality of intermediate voltages includes at least part of voltages obtained from one end of each of the plurality of non-linear resistor elements.

摘要翻译： 具有精确差分电压内插的闪存模数转换器，不使用硅化物阻挡电阻。 参考转换电压输出部分将基于多个参考电压的模拟输入电压转换为多个参考转换电压。 中间电压产生部分包括预定数量的非线性电阻单元，其分别设置在预定数量的多个基准转换电压中的成对中的一个电压和另一个电压之间，以通过使用预定的电压分压产生多个中间电压 非线性电阻单位数。 此外，中间电压产生部分产生多个转换电压。 数字数据输出部分使用双插值来输出基于多个转换电压的数字输出电压。 预定数量的非线性电阻单元中的每一个包括连接到一个电压的第一输入端子，连接到另一个电压的第二输入端子以及具有串联连接的相同电阻值的多个非线性电阻器元件 第一和第二输入端子。 多个中间电压包括从多个非线性电阻元件中的每一个的一端获得的电压的至少一部分。

公开(公告)号：US09240822B2

公开(公告)日：2016-01-19

申请号：US13528827

申请日：2012-06-20

申请人： Jeng-Shiann Jiang ,  Heng-Chih Lin

发明人： Jeng-Shiann Jiang ,  Heng-Chih Lin

IPC分类号： H04B1/10 ,  H04B3/54 ,  H04B1/719 ,  H04B7/155 ,  H04L25/02 ,  H04L27/26

CPC分类号： H04B3/542 ,  H04B1/719 ,  H04B7/15521 ,  H04B2203/5416 ,  H04B2203/5495 ,  H04L25/0226 ,  H04L27/2602

摘要： A method of arranging a frame for power reduction, utilized in a transmitter in a communication system is disclosed. The transmitter communicates with a receiver in the communication system. The method comprises generating a preamble with a first power level in the frame; arranging a header with the first power level after the preamble in the frame, wherein the header comprises information of a second power level; arranging an additional channel estimation (ACE) symbol with the second power level after the header in the frame; and arranging a first payload with the second power level after the ACE symbol in the frame.

摘要翻译： 公开了一种在通信系统的发射机中使用的布置用于功率降低的帧的方法。 发射机与通信系统中的接收机进行通信。 该方法包括在帧中产生具有第一功率电平的前同步码; 在所述帧中的所述前导码之后布置具有所述第一功率电平的头部，其中所述头部包括第二功率电平的信息; 在帧中的报头之后布置具有第二功率电平的附加信道估计（ACE）符号; 以及在所述帧中的ACE符号之后布置具有所述第二功率电平的第一有效载荷。

公开(公告)号：US20130044828A1

公开(公告)日：2013-02-21

申请号：US13528827

申请日：2012-06-20

申请人： Jeng-Shiann Jiang ,  Heng-Chih Lin

发明人： Jeng-Shiann Jiang ,  Heng-Chih Lin

IPC分类号： H04B3/54 ,  H04L27/28

CPC分类号： H04B3/542 ,  H04B1/719 ,  H04B7/15521 ,  H04B2203/5416 ,  H04B2203/5495 ,  H04L25/0226 ,  H04L27/2602

摘要： A method of arranging a frame for power reduction, utilized in a transmitter in a communication system is disclosed. The transmitter communicates with a receiver in the communication system. The method comprises generating a preamble with a first power level in the frame; arranging a header with the first power level after the preamble in the frame, wherein the header comprises information of a second power level; arranging an additional channel estimation (ACE) symbol with the second power level after the header in the frame; and arranging a first payload with the second power level after the ACE symbol in the frame.

摘要翻译： 公开了一种在通信系统的发射机中使用的布置用于功率降低的帧的方法。 发射机与通信系统中的接收机进行通信。 该方法包括在帧中产生具有第一功率电平的前同步码; 在所述帧中的所述前导码之后布置具有所述第一功率电平的头部，其中所述头部包括第二功率电平的信息; 在帧中的报头之后布置具有第二功率电平的附加信道估计（ACE）符号; 以及在所述帧中的ACE符号之后布置具有所述第二功率电平的第一有效载荷。

公开(公告)号：US07548120B2

公开(公告)日：2009-06-16

申请号：US11836206

申请日：2007-08-09

申请人： Tin-Sing Lam ,  Chao-Tung Yang ,  Heng-Chih Lin ,  Shou-Fang Chen ,  Sining Zhou

发明人： Tin-Sing Lam ,  Chao-Tung Yang ,  Heng-Chih Lin ,  Shou-Fang Chen ,  Sining Zhou

IPC分类号： H03L7/00

CPC分类号： G06F1/08 ,  H03L7/099

摘要： A frequency switching method is used to make switching among a plurality of frequency signal sources each providing a specific frequency range covering multiple bands. The method includes steps of providing a target frequency data; selecting one of the frequency signal sources to output a first clock signal; generating a first frequency data according to the clock signal of the first frequency to compare with the target frequency data; outputting a second clock signal with the highest band of another one of the frequency signal sources possessing a frequency range higher than that of the selected frequency signal source when the target frequency data is greater than the first frequency data; and outputting the second clock signal with the lowest band of the selected frequency signal source when the target frequency data is smaller than the first frequency data.

摘要翻译： 频率切换方法用于在多个频率信号源之间进行切换，每个频率信号源提供覆盖多个频带的特定频率范围。 该方法包括提供目标频率数据的步骤; 选择频率信号源之一以输出第一时钟信号; 根据所述第一频率的时钟信号产生第一频率数据，以与所述目标频率数据进行比较; 当所述目标频率数据大于所述第一频率数据时，输出具有所述频率信号源中的另一个的最高频带的第二时钟信号，所述频率信号源具有高于所选择的频率信号源的频率范围的频率范围; 以及当所述目标频率数据小于所述第一频率数据时，将所述第二时钟信号输出到所选频率信号源的最低频带。

公开(公告)号：US20080093463A1

公开(公告)日：2008-04-24

申请号：US11616022

申请日：2006-12-26

申请人： Wei Chang ,  Heng-Chih Lin ,  Henry Tin-Hang Yung

发明人： Wei Chang ,  Heng-Chih Lin ,  Henry Tin-Hang Yung

IPC分类号： G06K19/06

CPC分类号： G06K19/0723 ,  G06K7/0008 ,  G08B13/2417

摘要： An RFID tag is integrated with a processor of an electronic product for anti-theft purpose. The RFID tag receives an enable mark when the electronic product is checked out at a point of sale. Only when the processor receives the enable mark from the RFID tag can the start-up sequence of the electronic product be executed. An RFID tag is integrated with a sensor of an electronic product for data transmission purpose. Data measured by the sensor can be stored in the memory of the RFID tag and outputted via the antenna of the RFID tag.

摘要翻译： RFID标签与用于防盗目的的电子产品的处理器集成。 当电子产品在销售点检出时，RFID标签接收使能标记。 只有当处理器从RFID标签接收使能标记时，才能执行电子产品的启动顺序。 RFID标签与用于数据传输目的的电子产品的传感器集成。 由传感器测量的数据可以存储在RFID标签的存储器中，并通过RFID标签的天线输出。

公开(公告)号：US07286019B2

公开(公告)日：2007-10-23

申请号：US11031185

申请日：2005-01-07

申请人： Solti Peng ,  Chien-Chung Chen ,  Abdellatif Bellaouar ,  Heng-Chih Lin

发明人： Solti Peng ,  Chien-Chung Chen ,  Abdellatif Bellaouar ,  Heng-Chih Lin

IPC分类号： H03F3/04

CPC分类号： H03F1/30 ,  H03F3/189 ,  H03F2200/18 ,  H03F2200/456 ,  H03F2200/72

摘要： According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an inductor for providing a path to ground for direct current flowing through the transistor. According to another embodiment of the invention, a method for amplifying a signal by an amplifier includes generating a gate bias voltage indicative of a difference between a reference voltage and an output voltage of the amplifier, biasing the gate of the common-gate amplifier with the gate bias voltage, and blocking, by a passive device, alternating current signals from flowing from the source of the transistor to ground.

摘要翻译： 根据本发明的一个实施例，放大器包括栅极偏置电路，其可操作以产生栅极偏置电压和公共栅极放大器，该公共栅极放大器包括具有由栅极偏置电路的输出偏置的栅极的晶体管，并且源极连接到 电感器，用于为直流电流流过晶体管提供路径。 根据本发明的另一个实施例，一种用于放大放大器的信号的方法包括：生成指示放大器的参考电压和输出电压之间的差异的栅极偏置电压，使公共栅极放大器的栅极偏置 栅极偏置电压和被无源器件阻塞从晶体管的源极流到地的交流信号。

公开(公告)号：US07034579B2

公开(公告)日：2006-04-25

申请号：US10743571

申请日：2003-12-22

申请人： Jin-sheng Wang ,  Heng-Chih Lin ,  Chien-Chung Chen

发明人： Jin-sheng Wang ,  Heng-Chih Lin ,  Chien-Chung Chen

IPC分类号： H03K5/22

CPC分类号： G01R19/16557

摘要： A high-speed signal level detector employs the high gain and high bandwidth of an inverter to perform a comparison. The high-speed signal level detector is capable of achieving the desired high-speed level detection without demanding the substantial power consumption required when using either the averaging technique or a high bandwidth op-amp type comparator.

摘要翻译： 高速信号电平检测器采用逆变器的高增益和高带宽进行比较。 高速信号电平检测器能够实现期望的高速电平检测，而不需要使用平均技术或高带宽运算放大器型比较器所需的实质功耗。