公开(公告)号：US5354700A

公开(公告)日：1994-10-11

申请号：US96904

申请日：1993-07-26

申请人： Heng-Sheng Huang ,  Chun Y. Chang

发明人： Heng-Sheng Huang ,  Chun Y. Chang

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66742 ,  H01L29/78687 ,  Y10S148/15 ,  Y10S148/16

摘要： An FET thin film transistor is formed with a channel formed of a Si/Si.sub.1-x Ge.sub.x /Si three layer sandwich which serves as the carrier transfer channel. The percentage of germanium is preferably less than 30% and should be less than about 50%. The TFT can be structured as top gate, bottom gate or twin gate structure. The Si/Si.sub.1-x Ge/Si sandwich layer is processed in a continuous process under computer control.

摘要翻译： FET薄膜晶体管形成有由用作载流子传输通道的Si / Si1-xGex / Si三层夹层形成的沟道。 锗的百分比优选小于30％且应小于约50％。 TFT可以被构造为顶栅，底栅或双栅结构。 Si / Si1-xGe / Si夹心层在计算机控制下以连续的方式进行处理。

公开(公告)号：US6015746A

公开(公告)日：2000-01-18

申请号：US056530

申请日：1998-04-07

申请人： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

发明人： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66583 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/665

摘要： A method of fabricating a semiconductor device. On a semiconductor substrate comprising a device isolation structure and an active region isolated by the device isolation region, an oxide layer is formed and etched on the active region to form an opening, so that the active within the opening is exposed. A first spacer is formed on a side wall of the opening. A gate oxide layer is formed on the active region within the opening. A conductive layer is formed on the gate oxide layer, so that the opening is filled thereby. The oxide layer is removed. The exposed active region is lightly doped to form a lightly doped region by using the conductive layer and the first spacer as a mask. A second spacer is formed on a side wall of the first spacer and leaves a portion of the first spacer to be exposed. The exposed active region is heavily doped to form a source/drain region by using the conductive layer, the first spacer, and the second spacer as a mask. The first spacer is removed to define a gate, so that an air gap between the gate and the second spacer is formed.

摘要翻译： 一种制造半导体器件的方法。 在包括器件隔离结构和由器件隔离区隔离的有源区的半导体衬底上，在有源区上形成氧化层并蚀刻以形成开口，从而露出开口内的活性物质。 第一间隔件形成在开口的侧壁上。 栅极氧化层形成在开口内的有源区上。 在栅极氧化物层上形成导电层，从而填充开口。 去除氧化物层。 通过使用导电层和第一间隔物作为掩模，暴露的有源区域被轻掺杂以形成轻掺杂区域。 第二间隔件形成在第一间隔件的侧壁上并且留下待暴露的第一间隔件的一部分。 通过使用导电层，第一间隔件和第二间隔件作为掩模，暴露的有源区域被重掺杂以形成源极/漏极区域。 去除第一间隔物以限定栅极，从而形成栅极和第二间隔物之间​​的气隙。

公开(公告)号：US5659511A

公开(公告)日：1997-08-19

申请号：US643363

申请日：1996-05-06

申请人： Heng-Sheng Huang

发明人： Heng-Sheng Huang

IPC分类号： G01R31/30 ,  G11C29/50 ,  G11C7/00

CPC分类号： G01R31/3004 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5006

摘要： A method of measuring the leakage current of a DRAM capacitive junction involves the of following steps: A DRAM memory is formed on a semiconductor substrate. The DRAM memory comprises a plurality of RAM memory cells and a measuring memory cell. Each of the RAM memory cells and the measuring memory cell includes a transistor and a capacitor serially connected. The contact area of a bottom plate of the capacitor of the measuring memory cell is much larger than that of the RAM memory cells. A first junction leakage current value is measured while the transistor of the measuring memory cell is turned off. A second junction leakage current value is measured while the transistor of the measuring memory cell is turned on. The first junction leakage current value then is subtracted from the second junction leakage current value. By dividing the difference by the contact are of the bottom plate of the capacitor of the measuring memory cell, the capacitive junction leakage current value per unit area of the DRAM is obtained.

摘要翻译： 测量DRAM电容结的泄漏电流的方法包括以下步骤：在半导体衬底上形成DRAM存储器。 DRAM存储器包括多个RAM存储器单元和测量存储单元。 每个RAM存储器单元和测量存储单元包括串联连接的晶体管和电容器。 测量存储单元的电容器的底板的接触面积比RAM存储单元的接触面积大得多。 在测量存储单元的晶体管截止时测量第一结漏电流值。 在测量存储单元的晶体管导通时测量第二结漏电流值。 然后从第二结漏电流值中减去第一结漏电流值。 通过将差除以测量存储单元的电容器的底板的接触面积，获得DRAM的每单位面积的电容结漏电流值。

公开(公告)号：US5572147A

公开(公告)日：1996-11-05

申请号：US525060

申请日：1995-09-08

申请人： Heng-Sheng Huang ,  Kun-Lun Chen ,  Te-Sun Wu

发明人： Heng-Sheng Huang ,  Kun-Lun Chen ,  Te-Sun Wu

IPC分类号： G01R19/165 ,  H03K5/153 ,  H03K17/22 ,  H03K19/0948

CPC分类号： H03K17/223 ,  G01R19/16519 ,  H03K5/153

摘要： A voltage detector for determining the high or low status of a power supply output voltage, including a front-end detector and an inverting amplifier. The front-end detector includes a number of NMOS and PMOS transistors which constitute active loads. The voltage detector is inherently independent of device fabrication condition changes, as well as on the temperature variations.

摘要翻译： 用于确定电源输出电压的高或低状态的电压检测器，包括前端检测器和反相放大器。 前端检测器包括构成有源负载的多个NMOS和PMOS晶体管。 电压检测器固有地独立于器件制造条件变化以及温度变化。

公开(公告)号：US06197642B1

公开(公告)日：2001-03-06

申请号：US09028521

申请日：1998-02-24

申请人： Wen-Kuan Yeh ,  Heng-Sheng Huang

发明人： Wen-Kuan Yeh ,  Heng-Sheng Huang

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28079 ,  H01L29/495

摘要： A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer. Consequently, over-exposing the upper trench corner locations of a shallow trench isolation structure can be prevented, thereby avoiding current leakage problems.

摘要翻译： 一种用于制造栅极端子的方法，包括以下步骤：提供衬底，然后形成和图案化氧化物层以形成栅极区域。 接下来，在栅极区域形成栅氧化层和晶体硅层。 然后在栅极区域中沉积钨层，然后抛光钨层以形成用作栅电极的最终钨层。 最后，去除氧化物层。 本发明的方法能够控制所制造的栅极端子的尺寸。 此外，在栅极氧化物层上形成薄的晶体硅层有助于增加与金属层的结合强度，并且可以在较低的处理温度下形成栅电极。 因此，如此形成的栅极具有更高的质量，并且半导体的处理容易得多。 此外，在氧化物层的蚀刻操作期间，氮化硅层可以用作蚀刻停止层。 因此，可以防止浅沟槽隔离结构的上沟槽角部位的过度曝光，从而避免电流泄漏问题。

公开(公告)号：US5920783A

公开(公告)日：1999-07-06

申请号：US55692

申请日：1998-04-06

申请人： H. C. Tseng ,  Kun-Cho Chen ,  Heng-Sheng Huang

发明人： H. C. Tseng ,  Kun-Cho Chen ,  Heng-Sheng Huang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  Y10S257/90

摘要： A method of fabricating a MOSFET device in accordance with the present invention can protect the device from the short channel effect and decrease the resistance of a gate of the device. The fabricating method includes the following steps. A device including a substrate, an oxide layer, a gate and a lightly doped region is provided, wherein the oxide layer is formed on the substrate and the gate is formed on the oxide layer. A conducting layer is formed on the oxide layer, and the conducting layer is etched to form a first spacer. Then, the device is implanted to form a heavily doped region. A dielectric layer is deposited on the device, and the dielectric layer is etched to form a second spacer. The oxide layer is etched to expose part of the side walls of the gate. Then, a self-aligned silicide is further processed to complete the fabricating processes. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.

摘要翻译： 根据本发明的制造MOSFET器件的方法可以保护器件免于短沟道效应并降低器件栅极的电阻。 制造方法包括以下步骤。 提供了包括衬底，氧化物层，栅极和轻掺杂区域的器件，其中氧化物层形成在衬底上，并且栅极形成在氧化物层上。 在氧化物层上形成导电层，蚀刻导电层以形成第一间隔物。 然后，将器件植入以形成重掺杂区域。 在器件上沉积介电层，蚀刻电介质层以形成第二间隔物。 蚀刻氧化物层以暴露栅极的一部分侧壁。 然后，进一步处理自对准的硅化物以完成制造工艺。 结果，MOSFET器件在第一间隔物下方具有超浅结，以减少源/漏电阻并增加器件的工作速率。

公开(公告)号：US5637896A

公开(公告)日：1997-06-10

申请号：US537103

申请日：1995-09-29

申请人： Heng-Sheng Huang

发明人： Heng-Sheng Huang

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A process of fabricating an array of floating gate memory devices on a substrate comprises forming elongated spaced apart parallel ion implanted field implant regions in the substrate, forming elongated spaced apart parallel buried bit lines in the substrate orthogonally directed relative to the field implant regions, forming field oxide regions over the buried bit lines and field implant regions, and growing a silicon dioxide gate oxide layer having a thickness of from approximately 80 .ANG. to approximately 300 .ANG. between the field oxide regions, forming a plurality of first gate members from a first layer of polysilicon, the first gate members being disposed over the gate oxide layer, forming a layer of interpolysilicon dielectric over the first gate members having a thickness of approximately 150 .ANG., forming elongated second gate members from a second layer of polysilicon over the layer of interpolysilicon dielectric and over the first gate members, the second gate members extending generally perpendicular to buried bit lines.

摘要翻译： 在衬底上制造浮动栅极存储器器件阵列的工艺包括在衬底中形成细长的间隔开的平行离子注入场注入区域，在衬底中相对于场注入区域正交地形成细长间隔开的并行埋入位线，形成 在掩埋位线和场注入区域之上的场氧化物区域，并且在场氧化物区域之间生长厚度大约为80至大约300的二氧化硅栅极氧化物层，从第一层形成多个第一栅极部件 的多晶硅，所述第一栅极部件设置在所述栅极氧化物层的上方，在所述第一栅极部件上形成厚度约为150的多晶硅介质层，在所述多晶硅层上形成从第二多晶硅层延伸的第二栅极部件 电介质和第一栅极部件上的第二栅极 构件大致垂直于掩埋位线延伸。

公开(公告)号：US06008118A

公开(公告)日：1999-12-28

申请号：US59310

申请日：1998-04-13

申请人： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

发明人： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867

摘要： A method of forming a barrier layer is disclosed. The barrier layer is formed on the upper surface of the tungsten plug. The method of forming the barrier layer is mainly a nitridation reaction. The nitridation reaction makes use of NH.sub.3 plasma, N.sub.2 plasma and N.sup.+ implantation.

摘要翻译： 公开了形成阻挡层的方法。 阻挡层形成在钨丝塞的上表面上。 形成阻挡层的方法主要是氮化反应。 氮化反应使用NH3等离子体，N2等离子体和N +注入。

公开(公告)号：US5985717A

公开(公告)日：1999-11-16

申请号：US642944

申请日：1996-05-06

申请人： Heng-Sheng Huang

发明人： Heng-Sheng Huang

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L29/49 ,  H01L21/336

CPC分类号： H01L27/11253 ,  H01L21/28105 ,  H01L29/4983

摘要： Disclosed is a method of fabricating memory devices. By the method, a silicon nitride layer is used as a mask to form oxide layers on the lateral sides of the word lines through high-temperature heat treatment as source/drain annealing or oxidation. An etching process is subsequently used to remove the silicon nitride layer so as to expose the polysilicon layer on the word lines. After that, metal, preferably aluminum, is selectively grown the exposed polysilicon layer, which allows the resistance of the word lines to be significantly lowered thereby increasing access speed of the memory device.

摘要翻译： 公开了一种制造存储器件的方法。 通过该方法，使用氮化硅层作为掩模，通过作为源极/漏极退火或氧化的高温热处理在字线的侧面上形成氧化物层。 随后使用蚀刻工艺去除氮化硅层，以露出字线上的多晶硅层。 此后，选择性地生长金属，优选铝，暴露的多晶硅层，这允许字线的电阻显着降低，从而增加存储器件的存取速度。

公开(公告)号：US5926729A

公开(公告)日：1999-07-20

申请号：US877204

申请日：1997-06-17

申请人： Meng-Jin Tsai ,  Heng-Sheng Huang

发明人： Meng-Jin Tsai ,  Heng-Sheng Huang

IPC分类号： H01L21/8234 ,  H01L21/70

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： A method is provided for use in semiconductor fabrication processes for forming a plurality of gate oxide layers with various predefined thicknesses in mixed-mode or embedded circuits that are formed in a semiconductor substrate. In particular, the gate oxide layers of various predefined thicknesses are formed by means of separated growth, which allows all the gate oxide layers to be each formed in one single step, instead of combining two or more oxide layers as in conventional processes, so that the thicknesses can be more easily controllable to the desired levels. The quality of the thus-formed gate oxide layers can thus be better assured.

摘要翻译： 提供了一种在半导体制造工艺中使用的方法，用于在形成在半导体衬底中的混合模式或嵌入电路中形成具有各种预定厚度的多个栅极氧化物层。 特别地，通过分离的生长形成各种预定厚度的栅极氧化物层，这允许在一个单一步骤中形成所有栅极氧化物层，而不是如在常规工艺中组合两个或更多个氧化物层，使得 厚度可以更容易地控制到期望的水平。 因此可以更好地保证这样形成的栅极氧化物层的质量。