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公开(公告)号：US20190171592A1
公开(公告)日：2019-06-06
申请号：US16258781
申请日：2019-01-28
摘要： A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.
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公开(公告)号：US20170230180A1
公开(公告)日：2017-08-10
申请号：US15515258
申请日：2014-10-29
CPC分类号： H04L9/32 , G06F12/10 , G06F13/4022 , G06F21/62 , H04L12/6418 , H04L29/1283 , H04L61/6018 , H04L63/04 , H04L63/08 , H04L63/0876 , H04L63/10 , H04L63/101 , H04Q2213/13339
摘要： A receiver node receives, over a communication fabric, a transaction packet that includes an identifier of a sender node and an identifier of a process at the sender node, the transaction packet sent by the process for a transaction. The receiver node performs authentication for the transaction based on the identifier of the process and the identifier of the sender node.
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公开(公告)号：US20170322889A1
公开(公告)日：2017-11-09
申请号：US15527395
申请日：2014-11-25
IPC分类号： G06F12/1027
CPC分类号： G06F12/1027 , G06F12/023 , G06F12/0292 , G06F2212/1041 , G06F2212/68
摘要： In an example implementation according to aspects of the present disclosure, a computing system includes a memory resource having a plurality of memory resource regions and a plurality of computing resources. The plurality of computing resources are communicatively coupleable to the memory resource. Each computing node may include a native memory management unit to manage a native memory on the computing resource and a memory resource memory management unit to manage the memory resource region of the memory resource associated with the computing resource.
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公开(公告)号：US20170322876A1
公开(公告)日：2017-11-09
申请号：US15527620
申请日：2014-11-25
CPC分类号： G06F12/023 , G06F11/20 , G06F12/0284 , G06F12/0292 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F12/109 , G06F13/28 , G06F2212/1041 , G06F2212/68 , G06T11/60 , G11C16/10
摘要： In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.
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5.发明申请公开(公告)号：US20200379930A1
公开(公告)日：2020-12-03
申请号：US16425803
申请日：2019-05-29
摘要： Methods and systems support bridging between end devices conforming to a legacy bus specification and a host processor using an updated bus specification, for example the latest PCIe specification or Compute Express Link (CXL). A hardware bridge can serve as an intermediary between the legacy I/O devices and the host processor. The hardware bridge has a hardware infrastructure and performs a hardware virtualization of the legacy I/O devices such that their legacy hardware is emulated by a virtual interface. The hardware bridge can surface the virtual interface to the host processor, enabling these I/O devices to appear to the host processor as an end device communicating in accordance with the updated bus specification. The hardware virtualization can involve emulating the I/O devices using scalable I/O Virtualization (SIOV) queue pairs, providing flexible and efficient translation between the legacy and updated specifications.
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公开(公告)号：US10394707B2
公开(公告)日：2019-08-27
申请号：US15527620
申请日：2014-11-25
IPC分类号： G06F11/20 , G06F12/02 , G06F12/10 , G06F13/28 , G06T11/60 , G11C16/10 , G06F12/109 , G06F12/1027 , G06F12/1036
摘要： In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.
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公开(公告)号：US10210107B2
公开(公告)日：2019-02-19
申请号：US15518195
申请日：2014-10-29
摘要： A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.
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公开(公告)号：US20170300433A1
公开(公告)日：2017-10-19
申请号：US15518195
申请日：2014-10-29
IPC分类号： G06F13/16 , G06F15/78 , H04L12/911
CPC分类号： G06F13/1668 , G06F13/1694 , G06F15/7821 , H04L47/70
摘要： A memory controller of a sender node issues an instruction of a trans-fabric instruction set of instructions to a receiver node across a communication fabric that supports memory semantic operations, to cause a given transaction to be performed at the receiver node in response to the issued instruction.
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