公开(公告)号：US4967339A

公开(公告)日：1990-10-30

申请号：US179554

申请日：1988-04-08

申请人： Hiroaki Fukumaru ,  Soichi Takaya ,  Takayuki Morioka ,  Tadaaki Bandoh ,  Shinichiro Yamaguchi ,  Kenji Hirose

发明人： Hiroaki Fukumaru ,  Soichi Takaya ,  Takayuki Morioka ,  Tadaaki Bandoh ,  Shinichiro Yamaguchi ,  Kenji Hirose

IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/355

CPC分类号： G06F9/30014 ,  G06F9/342 ,  G06F9/3889

摘要： A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

摘要翻译： 处理器通过操作数有效地址计算单元执行流水线并行处理，用于计算执行指令所需的操作数有效地址和执行指令的指令执行单元。 执行64位宽的数据操作，使得在操作数有效地址单元中的算术装置中执行高阶32位操作，并且在指令执行单元中的另一个运算装置中执行低位32位操作。 进位从低位32位运算器传输到高位32位运算器件。 如此连接的算术装置可以作为运算装置执行数据操作的64位。

公开(公告)号：US5551007A

公开(公告)日：1996-08-27

申请号：US121449

申请日：1993-09-16

申请人： Yoshihiro Miyazaki ,  Yoshiaki Takahashi ,  Manabu Araoka ,  Soichi Takaya ,  Hiroaki Fukumaru

发明人： Yoshihiro Miyazaki ,  Yoshiaki Takahashi ,  Manabu Araoka ,  Soichi Takaya ,  Hiroaki Fukumaru

IPC分类号： G06F12/00 ,  G06F11/18 ,  G06F13/368 ,  G06F15/173 ,  G06F13/40

CPC分类号： G06F15/173 ,  G06F13/368

摘要： A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to access the common memory therein at the time of requesting a read access to a common memory. Other CPUs in the system do not contain common memories, but do include arrangements to access the common memory of the first or second CPU at the time of requesting a read access to a common memory.

摘要翻译： 提供了多个公共存储器系统，其中至少三个CPU共享至少两个公共存储器，每个公共存储器存储一个和相同的内容。 第一和第二CPU中的每一个包含两个公共存储器中的相应一个，并且在请求对公共存储器的读取访问时，第一和第二CPU中的每一个具有访问公共存储器的布置。 系统中的其他CPU不包含公共存储器，但是在请求对公共存储器的读取访问时，确实包括访问第一或第二CPU的公共存储器的布置。

公开(公告)号：US06249363B1

公开(公告)日：2001-06-19

申请号：US09115763

申请日：1998-07-15

申请人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

发明人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

IPC分类号： H04B1020

CPC分类号： H04B10/271 ,  G06F13/4022 ,  H04B10/27 ,  H04B10/278

摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

摘要翻译： 该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为 使总线同时由多个节点驱动。 虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光 没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。 光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。

公开(公告)号：US5276836A

公开(公告)日：1994-01-04

申请号：US639353

申请日：1991-01-10

申请人： Hiroaki Fukumaru ,  Siochi Takaya ,  Yoshihiro Miyazaki ,  Daniel M. McCarthy

发明人： Hiroaki Fukumaru ,  Siochi Takaya ,  Yoshihiro Miyazaki ,  Daniel M. McCarthy

IPC分类号： G06F12/08 ,  G06F13/28 ,  G06F15/167 ,  G06F13/00 ,  G06F13/20

CPC分类号： G06F13/28 ,  G06F12/0888 ,  G06F15/167

摘要： A data processing device which includes a common memory connecting mechanism which is located between a memory bus to which copyback cache is connected, and a common memory. The common memory connecting mechanism includes a slave type transfer mechanism which directly assesses the common memory bypassing the cache and processes thereof, and a data mover which transfers data between the common memory and main memory.

摘要翻译： 一种数据处理装置，其包括位于与其相连的存储总线之间的公共存储器连接机构和公共存储器。 公共存储器连接机构包括直接评估绕过高速缓存的公共存储器及其处理的从属类型传送机制，以及在公共存储器和主存储器之间传送数据的数据移动器。

公开(公告)号：US07558483B2

公开(公告)日：2009-07-07

申请号：US10897074

申请日：2004-07-23

申请人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

发明人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

IPC分类号： H04B10/00

CPC分类号： H04B10/271 ,  G06F13/4022 ,  H04B10/27 ,  H04B10/278

摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

摘要翻译： 该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为 使总线同时由多个节点驱动。 虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光 没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。 光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。

公开(公告)号：US06782202B2

公开(公告)日：2004-08-24

申请号：US09865584

申请日：2001-05-29

申请人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

发明人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

IPC分类号： H04B1020

CPC分类号： H04B10/271 ,  G06F13/4022 ,  H04B10/27 ,  H04B10/278

摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

公开(公告)号：US06216236B1

公开(公告)日：2001-04-10

申请号：US09188903

申请日：1998-11-10

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F1134

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。 每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。 三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。 此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

公开(公告)号：US5901281A

公开(公告)日：1999-05-04

申请号：US434288

申请日：1995-05-03

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G11C29/00 ,  G06F11/34

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G06F11/1641 ,  G06F11/18 ,  G06F11/185 ,  G06F11/20 ,  G11C29/74

摘要： A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线连接的多个处理单元。 每个处理单元在公共支撑板（PL）上具有三个或更多个处理器，并由公共时钟单元控制。 三个处理器执行相同的操作，并且通过比较三个处理器的操作来检测处理器中的故障。 如果一个处理器发生故障，则在更换整个处理单元之前，至少暂时在处理单元的其他两个处理器中继续操作。 此外，处理单元可以在时钟单元内具有多个时钟（A，B），具有切换装置，使得处理器通常从主时钟（A）接收时钟脉冲，但是从辅助时钟（B ）如果主时钟（A）失败。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 此外，多个高速缓冲存储器可以共同地连接到处理器，使得一个高速缓冲存储器的故障允许处理单元使用另一高速缓冲存储器继续操作。 可以通过直接比较来实现高速缓冲存储器的内容的一致性，并且还可以使用比较方法来使处理器的内部高速缓冲存储器中的数据与外部高速缓冲存储器中的数据不同。 协议的一致性还可以确保不同处理器单元的高速缓存中的数据总是正确的。

公开(公告)号：US5345566A

公开(公告)日：1994-09-06

申请号：US825063

申请日：1992-01-24

申请人： Masayuki Tanji ,  Yoshihiro Miyazaki ,  Hiroaki Fukumaru ,  Syoji Yamaguchi ,  Koji Masui ,  Hisao Ogawa

发明人： Masayuki Tanji ,  Yoshihiro Miyazaki ,  Hiroaki Fukumaru ,  Syoji Yamaguchi ,  Koji Masui ,  Hisao Ogawa

IPC分类号： G06F11/14 ,  G06F11/18 ,  G06F11/20 ,  G06F13/00 ,  G06F13/364 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4022 ,  G06F13/364

摘要： A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

摘要翻译： 一种用于控制双总线系统的方法和装置，即使双总线系统的总线之一发生故障，也能够实现高速和连续的操作。 该方法和装置具有双总线系统，连接到双总线系统的两个总线的多个电子电路和用于向多个电子电路之一提供总线使用允许信号的总线控制器，所选择的一个电子电路 根据从多个电子电路发出的请求数据传送的总线占用请求信号。 如果双总线系统的两个总线的总线占用请求信号来自一个选定的电子电路，并且仲裁器的输出一致，那么总线使用允许信号被提供给一个所选择的电子电路，以允许占用两条总线的 双总线系统。 在两条总线完成数据传输时，确定双总线系统的数据传输完成。 在出现故障时可以立即确保持续运转，能够实现计算机系统的高速运转。