公开(公告)号：US07067382B2

公开(公告)日：2006-06-27

申请号：US10853128

申请日：2004-05-26

申请人： Hiroaki Nakaoka ,  Kentaro Nakanishi ,  Hiroyuki Umimoto ,  Atsuhiro Kajiya

发明人： Hiroaki Nakaoka ,  Kentaro Nakanishi ,  Hiroyuki Umimoto ,  Atsuhiro Kajiya

IPC分类号： H01L21/336

CPC分类号： H01L21/823842

摘要： As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

摘要翻译： 作为用于激活注入到栅电极中的杂质的第一热处理，进行长时间的低温热处理，其中几乎不会发生多晶硅中每个晶粒中的硼扩散，并且发生每个晶体边界中的硼扩散。 接下来，作为第二热处理，进行其中发生在多晶硅层中的每个晶粒中的杂质扩散的短时间的高温处理，例如尖峰退火和闪光退火。

公开(公告)号：US20050003621A1

公开(公告)日：2005-01-06

申请号：US10853128

申请日：2004-05-26

申请人： Hiroaki Nakaoka ,  Kentaro Nakanishi ,  Hiroyuki Umimoto ,  Atsuhiro Kajiya

发明人： Hiroaki Nakaoka ,  Kentaro Nakanishi ,  Hiroyuki Umimoto ,  Atsuhiro Kajiya

IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823842

摘要： As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

摘要翻译： 作为用于激活注入到栅电极中的杂质的第一热处理，进行长时间的低温热处理，其中几乎不会发生多晶硅中每个晶粒中的硼扩散，并且发生每个晶体边界中的硼扩散。 接下来，作为第二热处理，进行其中发生在多晶硅层中的每个晶粒中的杂质扩散的短时间的高温处理，例如尖峰退火和闪光退火。

公开(公告)号：US20120238068A1

公开(公告)日：2012-09-20

申请号：US13486877

申请日：2012-06-01

申请人： Masafumi TSUTSUI ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi TSUTSUI ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

公开(公告)号：US20090050981A1

公开(公告)日：2009-02-26

申请号：US12170191

申请日：2008-07-09

申请人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L47/00

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

公开(公告)号：US20060202287A1

公开(公告)日：2006-09-14

申请号：US11429154

申请日：2006-05-08

申请人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L29/76

CPC分类号： H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

摘要翻译： 栅极电极形成在半导体区域之间，其间插入有栅极绝缘膜。 通过第一掺杂剂的扩散，在栅电极旁边的半导体区域的一部分中形成第一导电类型的扩展的高浓度掺杂剂扩散层。 通过重离子的扩散，在扩展的高浓度掺杂剂扩散层下形成第二导电类型的口袋掺杂剂扩散层。 口袋掺杂剂扩散层包括通过重离子分离而形成的分离部分。

公开(公告)号：US07091093B1

公开(公告)日：2006-08-15

申请号：US09662358

申请日：2000-09-15

申请人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L21/8236 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

摘要翻译： 栅极电极形成在半导体区域之间，其间插入有栅极绝缘膜。 通过第一掺杂剂的扩散，在栅电极旁边的半导体区域的一部分中形成第一导电类型的扩展的高浓度掺杂剂扩散层。 通过重离子的扩散，在扩展的高浓度掺杂剂扩散层下形成第二导电类型的口袋掺杂剂扩散层。 口袋掺杂剂扩散层包括通过重离子分离而形成的分离部分。

公开(公告)号：US06894520B2

公开(公告)日：2005-05-17

申请号：US10355068

申请日：2003-01-31

申请人： Kyoji Yamashita ,  Hiroyuki Umimoto ,  Mutsumi Kobayashi ,  Katsuhiro Ohtani ,  Tatsuya Kunikiyo ,  Katsumi Eikyu

发明人： Kyoji Yamashita ,  Hiroyuki Umimoto ,  Mutsumi Kobayashi ,  Katsuhiro Ohtani ,  Tatsuya Kunikiyo ,  Katsumi Eikyu

IPC分类号： G01R27/26 ,  G01R31/27 ,  G01R31/28 ,  G01R31/312 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G01R31/26

CPC分类号： G01R31/275 ,  G01R31/312

摘要： A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages V1 and V2, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

摘要翻译： CBCM测量装置包括PMIS晶体管，NMIS晶体管，连接到第一节点的第一参考导体部分，在第一和第二参考导体部分之间形成有虚拟电容器的第二参考导体部分，第一测试导体部分 连接到第二节点和第二测试导体部分，其中测试电容器形成在第一和第二测试导体部分之间。 通过使用控制电压V 1和V 2将晶体管导通/截止，并且基于流过第一和第二节点的电流来测量测试电容器中的目标电容器的电容。 通过例如增加虚拟电容来提高电容测量精度。

公开(公告)号：US20050054195A1

公开(公告)日：2005-03-10

申请号：US10900272

申请日：2004-07-28

申请人： Takato Handa ,  Hiroyuki Umimoto ,  Tetsuya Ueda

发明人： Takato Handa ,  Hiroyuki Umimoto ,  Tetsuya Ueda

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device includes: a lower interlayer dielectric film provided on a substrate; a lower interconnect made up of a lower barrier metal layer formed along a wall surface of a lower interconnect groove in the lower interlayer dielectric film, and a copper film; and an upper plug and an upper interconnect. The upper plug passes through a silicon nitride film and comes into contact with the copper film of the lower interconnect. The lower interconnect is provided with a large number of convex portions buried in concave portions of the lower interconnect groove. Thus, voids in the lower interconnect are also gettered by the convex portions. Accordingly, the concentration of voids in the contact area between the lower interconnect and the upper plug is relieved, and an increase in contact resistance is suppressed.

摘要翻译： 本发明的半导体器件包括：设置在基板上的下层间绝缘膜; 由沿下层间电介质膜的下互连槽的壁面形成的下阻挡金属层和铜膜构成的下互连件; 以及上部插头和上部互连件。 上塞通过氮化硅膜并与下互连的铜膜接触。 下部互连件设置有埋在下部互连槽的凹部中的大量凸部。 因此，下部互连件中的空隙也被凸起部分吸收。 因此，下部布线和上部插塞之间的接触区域中的空隙的浓度被释放，并且抑制了接触电阻的增加。

公开(公告)号：US07893501B2

公开(公告)日：2011-02-22

申请号：US12170191

申请日：2008-07-09

申请人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。

公开(公告)号：US07417289B2

公开(公告)日：2008-08-26

申请号：US11730988

申请日：2007-04-05

申请人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

发明人： Masafumi Tsutsui ,  Hiroyuki Umimoto ,  Kaori Akamatsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

摘要： A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased.

摘要翻译： 半导体器件包括由nMISFET的源极/漏极区域上的氧化硅膜形成的第一型内部应力膜和在pMISFET的源极/漏极区域上由TEOS膜形成的第二类型内部应力膜。 在nMISFET的沟道区域中，由于第一型内应力膜，电子的移动方向产生拉伸应力，使得电子的迁移率增加。 在pMISFET的沟道区域中，由于第二类型的内部应力膜，在孔的移动方向上产生压缩应力，使得孔的迁移率增加。