公开(公告)号：US20060202287A1

公开(公告)日：2006-09-14

申请号：US11429154

申请日：2006-05-08

申请人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L29/76

CPC分类号： H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

摘要翻译： 栅极电极形成在半导体区域之间，其间插入有栅极绝缘膜。 通过第一掺杂剂的扩散，在栅电极旁边的半导体区域的一部分中形成第一导电类型的扩展的高浓度掺杂剂扩散层。 通过重离子的扩散，在扩展的高浓度掺杂剂扩散层下形成第二导电类型的口袋掺杂剂扩散层。 口袋掺杂剂扩散层包括通过重离子分离而形成的分离部分。

公开(公告)号：US07091093B1

公开(公告)日：2006-08-15

申请号：US09662358

申请日：2000-09-15

申请人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L21/8236 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

摘要： A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

摘要翻译： 栅极电极形成在半导体区域之间，其间插入有栅极绝缘膜。 通过第一掺杂剂的扩散，在栅电极旁边的半导体区域的一部分中形成第一导电类型的扩展的高浓度掺杂剂扩散层。 通过重离子的扩散，在扩展的高浓度掺杂剂扩散层下形成第二导电类型的口袋掺杂剂扩散层。 口袋掺杂剂扩散层包括通过重离子分离而形成的分离部分。

公开(公告)号：US06432802B1

公开(公告)日：2002-08-13

申请号：US09662359

申请日：2000-09-15

申请人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Taiji Noda ,  Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L213205

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513

摘要： After a gate electrode has been formed over a semiconductor region with a gate insulating film interposed therebetween, an amorphous layer is formed in the semiconductor region by implanting heavy ions with a large mass into the semiconductor region using the gate electrode as a mask. Then, ions of a first dopant are implanted into the semiconductor region using the gate electrode as a mask. Next, a first annealing process is conducted on the semiconductor region at a temperature between 400° C. and 550° C., thereby making the amorphous layer recover into a crystalline layer. Subsequently, a second annealing process is conducted on the semiconductor region, thereby forming an extended high-concentration dopant diffused layer of a first conductivity type and a pocket dopant diffused layer of a second conductivity type. The extended high-concentration dopant diffused layer is formed to have a shallow junction by diffusing the first dopant, while the pocket dopant diffused layer is formed under the extended high-concentration dopant diffused layer by diffusing the heavy ions.

摘要翻译： 在半导体区域上形成栅极电极之后，在栅极绝缘膜之间形成栅电极之后，通过使用栅电极作为掩模，将具有大质量的重离子注入到半导体区域中，在半导体区域中形成非晶层。 然后，使用栅电极作为掩模，将第一掺杂剂的离子注入半导体区域。 接下来，在400℃〜550℃的温度下对半导体区域进行第一退火处理，由此使非晶层回复成晶体层。 随后，对半导体区域进行第二退火处理，从而形成第一导电类型的扩展高浓度掺杂剂扩散层和第二导电类型的袋式掺杂剂扩散层。 通过扩散第一掺杂剂，扩展的高浓度掺杂剂扩散层通过扩散第一掺杂剂而形成为浅结，而通过扩散重离子而在扩展的高浓度掺杂剂扩散层下方形成袋掺杂剂扩散层。

公开(公告)号：US06921933B2

公开(公告)日：2005-07-26

申请号：US10713221

申请日：2003-11-17

申请人： Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/66492

摘要： A gate electrode is formed on a semiconductor substrate with agate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

摘要翻译： 在半导体衬底上形成有栅电极，其间插有玛瑙绝缘膜。 在位于栅电极下方的半导体衬底的表面部分的区域中形成由第一导电型半导体层构成的沟道区。 在位于栅电极两侧的半导体衬底的表面部分的区域中形成各自由第二导电型杂质层构成的源/漏区。 第二导电型延伸区域形成在与源极/漏极区域接触的沟道区域和源极/漏极区域的相应上部之间。 第一导电型袋区域形成在沟道区域和与源极/漏极区域接触的源极/漏极区域的相应下部，并且与栅极绝缘膜间隔开。

公开(公告)号：US5633211A

公开(公告)日：1997-05-27

申请号：US347114

申请日：1994-11-23

申请人： Shinichi Imai ,  Yuka Terai ,  Masanori Fukumoto ,  Kousaku Yano ,  Hiroyuki Umimoto ,  Shinji Odanaka ,  Yasuo Mizuno

发明人： Shinichi Imai ,  Yuka Terai ,  Masanori Fukumoto ,  Kousaku Yano ,  Hiroyuki Umimoto ,  Shinji Odanaka ,  Yasuo Mizuno

IPC分类号： C23C16/40 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/02

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/0215 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/3105 ,  H01L21/31625 ,  H01L21/31629

摘要： The characteristic of semiconductor devices is satisfactorily maintained because the planarization of a dielectric film of a semiconductor device is carried out at a lower flow temperature. In the case of a silicon dioxide film being a dielectric film, a network structure is composed of atoms of silicon which serve as a main constituent, and of atoms of oxygen which serve as a sub-constituent of a matrix of the dielectric film. These oxygen atoms are replaced by non-bridging constituents such as atoms of halogen including fluorine. This breaks a bridge, via an oxygen atom, between the silicon atoms, at a position where such a replacement takes place. In consequence, the viscosity of the dielectric film falls with the flow temperature. If, for example, part of the oxygen in a BPSG film is substituted by fluorine, this allows the dielectric film to flow at a lower temperature of 850.degree. C. The short channel effects can be suppressed.

摘要翻译： 由于半导体器件的电介质膜的平坦化在较低的流动温度下进行，因此令人满意地保持半导体器件的特性。 在作为电介质膜的二氧化硅膜的情况下，网状结构由作为主要成分的硅原子和作为电介质膜的基体的副成分的氧原子构成。 这些氧原子被诸如卤素原子包括氟的非桥连组分替代。 在发生这种替换的位置上，这通过氧原子在硅原子之间断开桥。 因此，电介质膜的粘度随流动温度而下降。 例如，如果BPSG膜中的氧的一部分被氟取代，则允许电介质膜在850℃的较低温度下流动。可以抑制短的通道效应。

公开(公告)号：US5584964A

公开(公告)日：1996-12-17

申请号：US453806

申请日：1995-05-30

申请人： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

发明人： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

IPC分类号： H01L21/3105 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/3105 ,  H01L27/108 ,  H01L27/105 ,  Y10S148/133 ,  Y10S438/978

摘要： There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).

摘要翻译： 公开了一种制造半导体存储器件的方法。 在包括开关晶体管的半导体衬底上形成层间绝缘膜。 然后，形成到达开关晶体管的有源区的存储器节点图形。 通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值 平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。 然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。 然后，在BPSG膜上形成铝布线。 利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低 通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

公开(公告)号：US5455205A

公开(公告)日：1995-10-03

申请号：US34763

申请日：1993-03-19

申请人： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

发明人： Hiroyuki Umimoto ,  Shin Hashimoto ,  Shinji Odanaka

IPC分类号： H01L21/3105 ,  H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10852 ,  H01L21/3105 ,  H01L27/108 ,  H01L27/105 ,  Y10S148/133 ,  Y10S438/978

摘要： There is disclosed a method of producing a semiconductor memory device. An interlayer insulation film is formed on a semiconductor substrate including a switching transistor. Then, a memory node pattern reaching an active region of the switching transistor is formed. A cell plate electrode pattern is formed through an insulation film formed on the memory node in such a manner that a value obtained by subtracting a thickness of a polycrystalline silicon film for a cell plate electrode from an overlapping dimension of a memory node pattern and the cell plate electrode pattern is not less than two times larger and not more than ten times larger than a thickness of deposition of a BPSG film. Then, the BPSG film is deposited on an entire surface, and then is caused to viscously flow by a heat treatment. Then, an aluminum wiring is formed on the BPSG film. With this construction, a step of the aluminum wiring in a boundary region between a memory cell array portion and a peripheral circuit portion, or in a word line-backing contact forming region, is decreased, thereby preventing the lowering of the yield of the aluminum wiring which is caused by the cutting of the aluminum wiring and the remaining of a residue of etching for a contact-forming electrode (for example, tungsten).

摘要翻译： 公开了一种制造半导体存储器件的方法。 在包括开关晶体管的半导体衬底上形成层间绝缘膜。 然后，形成到达开关晶体管的有源区的存储器节点图形。 通过形成在存储节点上的绝缘膜形成单元板电极图案，使得通过从存储器节点图案和单元的重叠尺寸减去用于单元板电极的多晶硅膜的厚度而获得的值 平板电极图案不小于BPSG膜的沉积厚度的两倍以上且不大于十倍。 然后，将BPSG膜沉积在整个表面上，然后通过热处理使其粘稠流动。 然后，在BPSG膜上形成铝布线。 利用这种结构，在存储单元阵列部分和外围电路部分之间或字线 - 背衬接触形成区域中的边界区域中的铝布线的步骤减小，从而防止铝的收率降低 通过切割铝布线引起的布线和剩余的用于接触形成电极（例如钨）的蚀刻残留物。

公开(公告)号：US06667216B2

公开(公告)日：2003-12-23

申请号：US09996932

申请日：2001-11-30

申请人： Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/66492

摘要： A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

公开(公告)号：US06333217B1

公开(公告)日：2001-12-25

申请号：US09570391

申请日：2000-05-12

申请人： Hiroyuki Umimoto ,  Shinji Odanaka

发明人： Hiroyuki Umimoto ,  Shinji Odanaka

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/1083 ,  H01L29/66492

摘要： A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

摘要翻译： 在半导体衬底上形成栅电极，其间插入有栅极绝缘膜。 在位于栅电极下方的半导体衬底的表面部分的区域中形成由第一导电型半导体层构成的沟道区。 在位于栅电极两侧的半导体衬底的表面部分的区域中形成各自由第二导电型杂质层构成的源/漏区。 第二导电型延伸区域形成在与源极/漏极区域接触的沟道区域和源极/漏极区域的相应上部之间。 第一导电型袋区域形成在沟道区域和与源极/漏极区域接触的源极/漏极区域的相应下部，并且与栅极绝缘膜间隔开。

公开(公告)号：US06312981B1

公开(公告)日：2001-11-06

申请号：US09511045

申请日：2000-02-23

申请人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

发明人： Kaori Akamatsu ,  Shinji Odanaka ,  Hiroyuki Umimoto

IPC分类号： H01L218238

CPC分类号： H01L21/28185 ,  H01L21/2652 ,  H01L21/28211 ,  H01L21/324 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/105

摘要： A method for producing a semiconductor device includes the steps of: forming an impurity diffusion layer for controlling a threshold voltage by ion implantation; and conducting a high-temperature rapid heat treatment for recovering crystal defects generated by the ion implantation. More specifically, treatment conditions for the high-temperature rapid heat treatment are set in such a manner that interstitial atoms causing the crystal defects are diffused, and impurities in the impurity diffusion layer are not diffused. For example, the high-temperature rapid heat treatment is conducted in a temperature range of about 900° C. to about 1100° C.