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    Nonvolatile semiconductor storage device and its manufacturing method
    1.
    发明授权
    Nonvolatile semiconductor storage device and its manufacturing method 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US6117729A

    公开(公告)日：2000-09-12

    申请号：US97152

    申请日：1998-06-12

    申请人： Hirohisa Iizuka ,  Shinji Satoh ,  Riichiro Shirota

    发明人： Hirohisa Iizuka ,  Shinji Satoh ,  Riichiro Shirota

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.

    摘要翻译： 用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置 多个NAND存储器单元。 用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。

    Nonvolatile semiconductor storage device and its manufacturing method
    2.
    发明授权
    Nonvolatile semiconductor storage device and its manufacturing method 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US06288942B1

    公开(公告)日：2001-09-11

    申请号：US09632626

    申请日：2000-08-04

    申请人： Hirohisa Iizuka ,  Shinji Satoh ,  Riichiro Shirota

    发明人： Hirohisa Iizuka ,  Shinji Satoh ,  Riichiro Shirota

    IPC分类号： G11C1604

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

    摘要： High-concentrated impurity regions 24 for isolation of bit line contacts, having the same conduction type as that of a semiconductor substrate 10, are formed in the semiconductor substrate 10 under field oxide films 12 in locations between individual drain regions of selection transistors provided in a plurality of NAND memory cells, respectively. The high-concentrated impurity regions 24 for isolation of bit line contacts are made in a common step of making high-concentrated impurity regions 26 for isolation of memory transistors, by implanting impurities into the semiconductor substrate 10 through slits 20a, 20b made in a first conductive film 20. The high-concentrated impurity regions 24 prevent the punch-through phenomenon between bit line contacts 42a, and improve the resistivity to voltage between the bit line contacts 42a.

    摘要翻译： 用于隔离具有与半导体衬底10相同的导电类型的位线接触的高浓度杂质区24形成在半导体衬底10中的场氧化物膜12下的位于选择晶体管的各漏极区之间的位置 多个NAND存储器单元。 用于隔离位线触点的高浓度杂质区24是通过将杂质注入到半导体衬底10中的狭缝20a，20b以第一个方式制造的共同步骤制成用于隔离存储晶体管的高浓度杂质区26 高浓度杂质区24防止位线触点42a之间的穿通现象，并提高位线触点42a之间的电压电阻率。

    Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough
    4.
    发明授权
    Nonvolatile semiconductor memory device covered with insulating film which is hard for an oxidizing agent to pass therethrough 失效
    被绝缘膜覆盖的非易失性半导体存储器件，其难以氧化剂通过

    公开(公告)号：US06828624B1

    公开(公告)日：2004-12-07

    申请号：US09556777

    申请日：2000-04-25

    申请人： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

    发明人： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

    IPC分类号： H01L29792

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11543 ,  Y10S257/909

    摘要： A nonvolatile semiconductor memory device includes comprises: an element isolation region being in contact with a first element region, an insulating film covering a memory cell, a peripheral transistor and the element isolation region, an inter-level insulating film provided on the surface of the insulating film, and a contact hole provided in the inter-level insulating film and the insulating film. The inter-level insulating film contains an insulator different from the insulating film. The contact hole reaches at least one of source and drain diffusion layers of the memory cell and overlaps the element isolation region. The insulating film contains an insulator different from the element isolation region and the insulating film is harder for an oxidizing agent to pass therethrough than a silicon oxide film. A surface of the insulating film is oxidized.

    摘要翻译： 非易失性半导体存储器件包括：与第一元件区域接触的元件隔离区域，覆盖存储单元的绝缘膜，外围晶体管和元件隔离区域，设置在第一元件区域的表面上的层间绝缘膜 绝缘膜和设置在层间绝缘膜和绝缘膜中的接触孔。 层间绝缘膜含有与绝缘膜不同的绝缘体。 接触孔到达存储单元的源极和漏极扩散层中的至少一个并且与元件隔离区域重叠。 绝缘膜含有与元件隔离区不同的绝缘体，绝缘膜比氧化硅膜更难以通过氧化剂。 绝缘膜的表面被氧化。

    Semiconductor device and method of manufacturing the same
    8.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06828648B2

    公开(公告)日：2004-12-07

    申请号：US10655122

    申请日：2003-09-04

    申请人： Naoki Koido ,  Riichiro Shirota ,  Hirohisa Iizuka

    发明人： Naoki Koido ,  Riichiro Shirota ,  Hirohisa Iizuka

    IPC分类号： H01L2900

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： In a method of manufacturing a semiconductor device of STI structure, a semiconductor structure in which an insulating material layer is formed on a conductive layer which becomes a gate electrode, is prepared. Etching is conducted to the semiconductor structure to form a trench extending from the insulating material layer into the semiconductor substrate in accordance with a pattern of a resist film (not shown) covering an element region. Then, the insulating material layer is backed off by wet etching or the like and the gate electrode is processed while using the insulating material layer as a mask. As a result, it is possible to make the gate electrode smaller in size than the element region and to form a trench upper portion to be wider than the trench lower portion in the depth direction of the trench, thereby providing a good shape of the insulator embedded in the trench by depositing the insulator.

    摘要翻译： 在制造STI结构的半导体器件的方法中，准备了在形成栅电极的导电层上形成绝缘材料层的半导体结构。 根据覆盖元件区域的抗蚀剂膜（未示出）的图案，对半导体结构进行蚀刻以形成从绝缘材料层延伸到半导体衬底中的沟槽。 然后，通过湿式蚀刻等使绝缘材料层退回，并且在使用绝缘材料层作为掩模的同时对栅电极进行加工。 结果，可以使栅电极的尺寸小于元件区域，并且在沟槽的深度方向上形成比沟槽下部更宽的沟槽上部，从而提供绝缘体的良好形状 通过沉积绝缘体嵌入在沟槽中。

    Nonvolatile semiconductor memory device and method for manufacturing the same
    9.
    发明授权
    Nonvolatile semiconductor memory device and method for manufacturing the same 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US06747311B2

    公开(公告)日：2004-06-08

    申请号：US10145122

    申请日：2002-05-15

    申请人： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

    发明人： Akira Goda ,  Riichiro Shirota ,  Kazuhiro Shimizu ,  Hiroaki Hazama ,  Hirohisa Iizuka ,  Seiichi Aritome ,  Wakako Moriyama

    IPC分类号： H01L29788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11543 ,  Y10S257/909

    摘要： A nonvolatile semiconductor memory device includes memory cell transistors, peripheral transistors, first post-oxidation films provided on the gate electrode of all of the memory cell transistors, second post-oxidation films provided on the gate electrode of all of the peripheral transistors, first insulating films provided on the first post-oxidation films and covering a side surface of the gate electrode of all of the memory cell transistors and second insulating films provided on the second post-oxidation films and covering a side surface of the gate electrode of all of the peripheral transistors. The first and second insulating films are harder for an oxidizing agent to pass therethrough than a silicon oxide film, and the first and second insulating films are oxidized.

    摘要翻译： 非易失性半导体存储器件包括存储单元晶体管，外围晶体管，设置在所有存储单元晶体管的栅电极上的第一后氧化膜，设置在所有外围晶体管的栅电极上的第二后氧化膜，第一绝缘 提供在第一后氧化膜上并覆盖所有存储单元晶体管的栅电极的侧表面的膜和设置在第二后氧化膜上的第二绝缘膜，并覆盖所有栅极电极的侧表面 外围晶体管。 第一绝缘膜和第二绝缘膜比氧化硅膜更难以通过氧化剂，并且第一和第二绝缘膜被氧化。