公开(公告)号：US06828627B2

公开(公告)日：2004-12-07

申请号：US10742952

申请日：2003-12-23

申请人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

发明人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

公开(公告)号：US06703669B1

公开(公告)日：2004-03-09

申请号：US09714228

申请日：2000-11-17

申请人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

发明人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

公开(公告)号：US20050073008A1

公开(公告)日：2005-04-07

申请号：US10993448

申请日：2004-11-22

申请人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

发明人： Akira Goda ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Norihisa Arai ,  Naoki Koido ,  Seiichi Aritome ,  Tohru Maruyama ,  Hiroaki Hazama ,  Hirohisa Iizuka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L23/62

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor device exhibits a stable driving force and high performance reliability. The semiconductor device has at least one transistor having a gate insulating film formed on a element region in a semiconductor substrate, a gate electrode formed on the gate insulating film, and a diffused layer in element regions on both sides of the gate electrode. The device also has a barrier insulating film formed so as to cover the transistor and the diffused layer. The height from a surface of the semiconductor substrate to the barrier insulating film is greater than the height from the surface, of the interface between the gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有稳定的驱动力和高性能的可靠性。 半导体器件具有至少一个晶体管，其具有形成在半导体衬底中的元件区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅极电极和在栅电极两侧的元件区域中的扩散层。 该器件还具有形成为覆盖晶体管和扩散层的阻挡绝缘膜。 从半导体衬底的表面到阻挡绝缘膜的高度大于栅极绝缘膜和栅电极之间的界面的表面的高度。

公开(公告)号：US06680230B2

公开(公告)日：2004-01-20

申请号：US10201111

申请日：2002-07-24

申请人： Norihisa Arai ,  Fumitaka Arai ,  Seiichi Aritome ,  Akira Shimizu ,  Riichiro Shirota

发明人： Norihisa Arai ,  Fumitaka Arai ,  Seiichi Aritome ,  Akira Shimizu ,  Riichiro Shirota

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of fabricating a semiconductor device which has a cell array with non-volatile memory transistors and a peripheral circuit including a first transistor and a second transistor as driven by a lower voltage than the first transistor is disclosed. The method includes the steps of forming over a semiconductor substrate a first gate dielectric film for use in the first transistor, selectively etching the first gate dielectric film in the cell array region to expose the substrate, forming over the exposed substrate a second gate dielectric film which is for use as a tunnel dielectric film of the memory transistors, forming a first gate electrode material film over the first and second gate dielectric films, selectively etching the first gate electrode material film and its underlying first gate dielectric film in the second transistor region, forming over the exposed substrate a third gate dielectric film which is for use in the second transistor, forming a second gate electrode material film over the third gate dielectric film, and forming gates of the respective transistors while letting the gates at least partly include the first and second gate electrode material films.

摘要翻译： 公开了一种制造半导体器件的方法，该半导体器件具有具有非易失性存储晶体管的单元阵列和包括由比第一晶体管低的电压驱动的第一晶体管和第二晶体管的外围电路。 该方法包括以下步骤：在半导体衬底上形成用于第一晶体管的第一栅极电介质膜，选择性地蚀刻电池阵列区域中的第一栅极电介质膜以暴露衬底，在暴露的衬底上形成第二栅极电介质膜 其用作存储晶体管的隧道电介质膜，在第一和第二栅极电介质膜上形成第一栅电极材料膜，在第二晶体管区域中选择性地蚀刻第一栅电极材料膜及其下面的第一栅极电介质膜 在暴露的衬底上形成用于第二晶体管的第三栅极电介质膜，在第三栅极电介质膜上形成第二栅电极材料膜，并且在使栅极至少部分地包括 第一和第二栅电极材料膜。

公开(公告)号：US20060202285A1

公开(公告)日：2006-09-14

申请号：US11403872

申请日：2006-04-14

申请人： Eiji Kamiya ,  Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Yuji Takeuchi ,  Norihisa Arai

发明人： Eiji Kamiya ,  Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Yuji Takeuchi ,  Norihisa Arai

IPC分类号： H01L29/76 ,  H01L21/82

CPC分类号： H01L27/11526 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/78

摘要： A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

公开(公告)号：US06534867B1

公开(公告)日：2003-03-18

申请号：US09670990

申请日：2000-09-26

申请人： Eiji Kamiya ,  Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Yuji Takeuchi ,  Norihisa Arai

发明人： Eiji Kamiya ,  Toshitake Yaegashi ,  Kazuhiro Shimizu ,  Riichiro Shirota ,  Yuji Takeuchi ,  Norihisa Arai

IPC分类号： H01L2348

CPC分类号： H01L27/11526 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/78

摘要： A semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.

摘要翻译： 半导体器件包括：半导体衬底; 多个具有低杂质浓度的第一扩散层，所述第一扩散层形成在所述半导体衬底的表面上; 多个具有高杂质浓度的第二扩散层，所述第二扩散层形成在所述半导体衬底的表面上; 多个第一触点，每个接触第一扩散层，并且每一个都由半导体形成; 以及多个第二触点，每个第二触点与第二扩散层接触，并且每个都由金属形成。

公开(公告)号：US07238563B2

公开(公告)日：2007-07-03

申请号：US10793923

申请日：2004-03-08

申请人： Norihisa Arai ,  Takeshi Nakano ,  Koki Ueno ,  Akira Shimizu

发明人： Norihisa Arai ,  Takeshi Nakano ,  Koki Ueno ,  Akira Shimizu

IPC分类号： H01L21/336

CPC分类号： H01L21/823481 ,  H01L21/2652 ,  H01L21/76237 ,  H01L29/0619 ,  H01L29/78

摘要： A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

摘要翻译： 沟槽隔离区域形成在半导体衬底的表面区域中以形成MOS型元件区域。 具有开口部的掩模层形成在半导体层上，开口部在MOS型元件区域的整个表面和设置在MOS型元件区域周围的沟槽隔离区域的一部分上连续地范围。 通过掩模层将第一杂质离子注入整个表面，以形成杂质分布的峰位于浅沟槽隔离区的底表面下的半导体层中。 通过掩模层将第二杂质离子注入整个表面以形成杂质分布的峰位于沟槽隔离区的深度方向的中间。 然后，第一和第二杂质离子被激活。

公开(公告)号：US06927116B2

公开(公告)日：2005-08-09

申请号：US10011777

申请日：2001-12-11

申请人： Norihisa Arai

发明人： Norihisa Arai

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/10 ,  H01L27/115 ,  H01L21/00

CPC分类号： H01L21/823892 ,  H01L27/0928

摘要： A first well of the same conductivity type as that of a semiconductor substrate and a second well of a conductivity type opposite to that of the semiconductor substrate, are formed in the semiconductor substrate. The second well isolates the semiconductor substrate and the first well from each other. Phosphorus ions for forming the bottom of the second well are implanted into the semiconductor substrate more deeply than boron ions for forming the first well. The depths to which these ions are implanted can be varied by acceleration energy of the ions. If the ions are so implanted, the total sum of impurities constituting the second well can be decreased within the surface area of the first well.

摘要翻译： 在半导体衬底中形成与半导体衬底相同的导电类型的第一阱和与半导体衬底相反的导电类型的第二阱。 第二阱将半导体衬底和第一阱彼此隔离。 用于形成第二阱的底部的磷离子比用于形成第一阱的硼离子更深地注入到半导体衬底中。 这些离子注入的深度可以通过离子的加速能来改变。 如果离子如此注入，则可以在第一阱的表面积内减少构成第二阱的杂质的总和。

公开(公告)号：US6034567A

公开(公告)日：2000-03-07

申请号：US30776

申请日：1998-02-26

申请人： Akira Umezawa ,  Shigeru Atsumi ,  Norihisa Arai ,  Hironori Banba ,  Ryo Sudo

发明人： Akira Umezawa ,  Shigeru Atsumi ,  Norihisa Arai ,  Hironori Banba ,  Ryo Sudo

IPC分类号： G11C11/419 ,  G05F3/24 ,  G05F3/30 ,  G11C11/409 ,  G11C11/413 ,  H01L21/8234 ,  H01L27/088 ,  H03F3/45 ,  H03F3/14

CPC分类号： H03F3/45479

摘要： A differential amplifier comprises an n-channel MOS transistor to the gate of which an input voltage VIN1 is fed, and an n-channel MOS transistor to the gate of which an input voltage VIN2 is fed. A p-channel MOS transistor arranged in such a manner that, to the source thereof, a power source voltage Vcc is fed, and the gate and drain thereof are connected to the drain of the MOS transistor, and a p-channel MOS transistor arranged in such a manner that the gate thereof is connected to the drain of the MOS transistor, the drain thereof is connected to the drain of the MOS transistor, and the voltage at this drain is outputted as an output voltage VOUT, and the output current I of a constant-current source is set so that the transistors constituting a differential amplifier may operate in a weak inversion zone.

摘要翻译： 差分放大器包括输入电压VIN1的栅极的n沟道MOS晶体管和馈入输入电压VIN2的栅极的n沟道MOS晶体管。 一个p沟道MOS晶体管，以这样一种方式被布置：从源极输入电源电压Vcc，其栅极和漏极连接到MOS晶体管的漏极，并配置有p沟道MOS晶体管 以其栅极连接到MOS晶体管的漏极，其漏极连接到MOS晶体管的漏极，并且该漏极处的电压作为输出电压VOUT输出，并且输出电流I 设置恒流源，使得构成差分放大器的晶体管可以在弱反转区域中工作。

公开(公告)号：US08399953B2

公开(公告)日：2013-03-19

申请号：US12885031

申请日：2010-09-17

申请人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Yoshiko Kato ,  Norihisa Arai ,  Tomoaki Hatano

发明人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Yoshiko Kato ,  Norihisa Arai ,  Tomoaki Hatano

IPC分类号： H01L29/00 ,  H01L29/167 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor device includes a semiconductor substrate, an element isolation insulating film dividing an upper portion of the substrate into a plurality of first active regions, a source layer and a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The source layer and the drain layer are formed in spaced to each other in an upper portion of each of the first active regions. The first punch-through stopper layer is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region.

摘要翻译： 半导体器件包括半导体衬底，将衬底的上部分成多个第一有源区的元件隔离绝缘膜，源极层和漏极层，栅极电极，栅极绝缘膜，第一穿通 阻挡层和第二穿通止挡层。 源极层和漏极层在每个第一有源区域的上部彼此间隔开地形成。 第一穿通阻挡层形成在源层正下方的第一有源区的区域中，并且第二穿通阻挡层形成在漏极层正下方的第一有源区的区域中。 第一穿通阻止层和第二穿通阻止层各自具有高于半导体衬底的有效杂质浓度。 第一穿通阻止层和源极层在沟道区域中分离。 第二穿通阻止层和漏极层在沟道区域中分离。