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103 条记录 (耗时 0.02 秒)

    Device for canceling interference
    1.
    发明授权
    Device for canceling interference 失效
    消除干扰的设备

    公开(公告)号：US06967991B1

    公开(公告)日：2005-11-22

    申请号：US09701535

    申请日：2000-03-28

    申请人： Hiroki Haga ,  Mitsuru Uesugi ,  Katsuhiko Hiramatsu

    发明人： Hiroki Haga ,  Mitsuru Uesugi ,  Katsuhiko Hiramatsu

    IPC分类号： H04J13/00 ,  H04B1/10 ,  H04B1/7107 ,  H04B1/707

    CPC分类号： H04B1/71075 ,  H04B1/7115 ,  H04B1/712

    摘要： A delay device 102 sends reception signals to a subtraction device 113 after delaying it by a predetermined time. Matched filters 103-1˜103-N perform despreading operation of the reception signals. RAKE-combining devices 104-1˜104-N perform RAKE-combining operation of the signals after the despreading operation. Discrimination devices 105-1˜105-N perform hard decision of the signals after the RAKE-combining operation. A decision value buffer 107 stores the signals after the hard decision. Likelihood calculation devices 106-1˜106-N calculate likelihood of all the symbols. A likelihood buffer 108 stores calculated likelihood. A controlling part 110 controls a switch 109. A ranking decision device 111 decides a ranking based on the likelihood. A re-spreading device 112 performs re-spreading operation of a symbol with the highest likelihood ranking. And a subtraction device 113 subtracts the re-spreading result from the delayed reception signals.

    摘要翻译： 延迟装置102在将其延迟预定时间之后将接收信号发送到减法装置113。 匹配滤波器103-1〜103 -N执行接收信号的解扩操作。 RAKE组合设备104-1〜104 -N在解扩操作之后执行信号的RAKE组合操作。 识别装置105-1〜105 -N在RAKE组合操作之后执行信号的硬判决。 决策值缓冲器107存储硬判决之后的信号。 似然计算装置106-1〜106 -N计算所有符号的可能性。 似然缓冲器108存储计算的似然性。 控制部分110控制开关109。 排序决定装置111根据似然性判定排序。 重新扩展装置112执行具有最高似然等级的符号的重新扩展操作。 并且减法装置113从延迟的接收信号中减去再扩频结果。

    Synchronization equipment
    2.
    发明授权
    Synchronization equipment 失效
    同步设备

    公开(公告)号：US06456677B1

    公开(公告)日：2002-09-24

    申请号：US09709650

    申请日：2000-11-13

    申请人： Katsuhiko Hiramatsu ,  Mitsuru Uesugi ,  Hiroaki Sudo

    发明人： Katsuhiko Hiramatsu ,  Mitsuru Uesugi ,  Hiroaki Sudo

    IPC分类号： H04L700

    CPC分类号： H04L7/0054 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/041

    摘要： The synchronizing apparatus includes a block for detecting a code from an input signal, a block for detecting from the code the variable points of the code at several times as high as the symbol rate, a block for calculating a histogram of the detected variables of the code to time, and a block for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. This synchronizing apparatus detects the zero-cross points of an intermediate frequency band signal at N times as high as the symbol rate. It also calculates a histogram of detected time (0 to N−1). The time (0 to N−1) at which the histogram is the maximum within a predetermined detected time is selected as a symbol clock, and thereby symbol synchronization is established.

    摘要翻译： 同步装置包括用于从输入信号中检测代码的块，用于从代码中检测代码的可变点数为符号速率的几倍的块，用于计算检测到的变量的直方图的块 代码到时间，以及用于确定计算的直方图获取最大值的相位数的块是符号同步点。 该同步装置检测中间频带信号的零交叉点的N倍于符号率。 它还计算检测时间的直方图（0到N-1）。 选择在预定检测时间内直方图为最大值的时间（0到N-1）作为符号时钟，从而建立符号同步。

    CMA-based antenna system
    3.
    发明授权
    CMA-based antenna system 失效
    基于CMA的天线系统

    公开(公告)号：US5907303A

    公开(公告)日：1999-05-25

    申请号：US873705

    申请日：1997-06-12

    申请人： Hideki Yukitomo ,  Mitsuru Uesugi ,  Katsuhiko Hiramatsu

    发明人： Hideki Yukitomo ,  Mitsuru Uesugi ,  Katsuhiko Hiramatsu

    IPC分类号： H04L27/22 ,  G01S3/02 ,  G01S3/06 ,  H01Q3/26 ,  H04B7/005 ,  H04B7/08 ,  H04L1/02 ,  G01S3/16

    CPC分类号： H01Q3/2605 ,  G01S3/06 ,  H04B7/0845 ,  G01S3/023

    摘要： A CMA-based antenna system is disclosed which shows an improved receiving performance by reducing phase differences in the received signals which have been weighted. The CMA-based antenna system comprises a plurality of antenna, weight circuits, an adder, an error detector and a synthesis controller. The synthesis controller controls the weight circuits so as not only to make the adder output at a preset level but also to cause any differences among the weight circuit outputs not to increase. In order to cope with an error of symbol synchronization and a delayed wave, the CMA-based antenna system may further have a kind of equalizer inserted before the weight circuit in each antenna circuit.

    摘要翻译： 公开了一种基于CMA的天线系统，其通过减少已经被加权的接收信号中的相位差来显示改进的接收性能。 基于CMA的天线系统包括多个天线，加权电路，加法器，误差检测器和综合控制器。 合成控制器控制加权电路，不仅使加法器的输出处于预设电平，而且也使得加权电路输出之间的任何差异不增加。 为了应对符号同步和延迟波的误差，基于CMA的天线系统还可以在每个天线电路中的加权电路之前进一步插入一种均衡器。

    Transmission apparatus
    4.
    发明授权
    Transmission apparatus 失效
    传输装置

    公开(公告)号：US06522869B1

    公开(公告)日：2003-02-18

    申请号：US09446082

    申请日：1999-12-17

    申请人： Katsuhiko Hiramatsu ,  Mitsuru Uesugi ,  Masatoshi Watanabe ,  Toyoki Ue

    发明人： Katsuhiko Hiramatsu ,  Mitsuru Uesugi ,  Masatoshi Watanabe ,  Toyoki Ue

    IPC分类号： H04B104

    CPC分类号： H04L27/2623 ,  H04L5/0016 ,  H04L5/06 ,  H04L27/2602

    摘要： Signals subjected to orthogonal modulation with a plurality of carrier frequencies are added to detect peak power. Based on the peak power, a coefficient for suppressing an amplitude of a transmission baseband signal is calculated. Using the coefficient, the amplitude of a baseband signal to be inputted to a filter is suppressed. It is thereby possible to suppress the peak power assuredly, and by the effects of the filter, unnecessary frequencies are not generated.

    摘要翻译： 加入经受多个载频的正交调制的信号，以检测峰值功率。 基于峰值功率，计算用于抑制发送基带信号的振幅的系数。 使用该系数，抑制要输入到滤波器的基带信号的幅度。 从而可以可靠地抑制峰值功率，并且通过滤波器的效果，不产生不必要的频率。

    Differential detector with error correcting function
    5.
    发明授权
    Differential detector with error correcting function 失效
    差分检测器，具有纠错功能

    公开(公告)号：US6069924A

    公开(公告)日：2000-05-30

    申请号：US27510

    申请日：1998-02-20

    申请人： Hiroaki Sudo ,  Katsuhiko Hiramatsu ,  Mitsuru Uesugi

    发明人： Hiroaki Sudo ,  Katsuhiko Hiramatsu ,  Mitsuru Uesugi

    IPC分类号： H04L27/22 ,  H04L1/00 ,  H04L27/227 ,  H04L27/233

    CPC分类号： H04L1/0047 ,  H04L27/2332

    摘要： A differential detector imparted with error correcting function for detecting a differentially phase shifted signal while performing error correction includes a one-symbol differential detector for performing phase comparison between a current input signal and a signal preceding by one symbol, a delay circuit for delaying a one-symbol differential detection signal by two symbol periods, a two-symbol differential detector for performing phase comparison between the current input signal and an input signal preceding by two symbol periods, a four-symbol differential detector for performing phase comparison between the current input signal and an input signal preceding by four symbol periods, and two error correction circuits. By making use of the four-symbol differential detection signal, error correction of the two-symbol differential detection signal is performed by the error correction circuit while error correction of the one-symbol differential detection signal is performed by using the corrected two-symbol differential detection signal. By diminishing the error of the two-symbol differential detection signal, the error correcting capability for the one-symbol differential detection signal is enhanced with bit error rate characteristic being improved.

    摘要翻译： 具有用于在执行纠错时检测差分相移信号的误差校正功能的差分检测器包括一个符号差分检测器，用于执行当前输入信号和一个符号之前的信号之间的相位比较;延迟电路，用于延迟一个 符号差分检测信​​号，两个符号周期的两符号差分检测器，用于执行当前输入信号和两个符号周期之前的输入信号之间的相位比较的双符号差分检测器，用于执行当前输入信号 和四个符号周期之前的输入信号，以及两个误差校正电路。 通过利用四符号差分检测信​​号，通过纠错电路执行两符号差分检测信​​号的纠错，同时通过使用校正的两符号差分进行一符号差分检测信​​号的纠错 检测信号。 通过减小二符号差分检测信​​号的误差，增加了单码元差分检测信​​号的误码校正能力，改善了误码率特性。

    Synchronizing apparatus
    6.
    发明授权
    Synchronizing apparatus 失效
    同步装置

    公开(公告)号：US06208701B1

    公开(公告)日：2001-03-27

    申请号：US08867806

    申请日：1997-06-03

    申请人： Katsuhiko Hiramatsu ,  Mitsuru Uesugi ,  Hiroaki Sudo

    发明人： Katsuhiko Hiramatsu ,  Mitsuru Uesugi ,  Hiroaki Sudo

    IPC分类号： H04L700

    CPC分类号： H04L7/0054 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/041

    摘要： The synchronizing apparatus includes a block for detecting a code from an input signal, a block for detecting from the code the variable points of the code at several times as high as the symbol rate, a block for calculating a histogram of the detected variables of the code to time, and a block for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. This synchronizing apparatus detects the zero-cross points of an intermediate frequency band signal at N times as high as the symbol rate. It also calculates a histogram of detected time (0 to N−1). The time (0 to N−1) at which the histogram is the maximum within a predetermined detected time is selected as a symbol clock, and thereby symbol synchronization is established.

    摘要翻译： 同步装置包括用于从输入信号中检测代码的块，用于从代码中检测代码的可变点数为符号速率的几倍的块，用于计算检测到的变量的直方图的块 代码到时间，以及用于确定计算的直方图获取最大值的相位数的块是符号同步点。 该同步装置检测中间频带信号的零交叉点的N倍于符号率。 它还计算检测时间的直方图（0到N-1）。 选择在预定检测时间内直方图为最大值的时间（0到N-1）作为符号时钟，从而建立符号同步。

    Estimator of error rate
    7.
    发明授权
    Estimator of error rate 失效
    估计误差率

    公开(公告)号：US6111921A

    公开(公告)日：2000-08-29

    申请号：US28853

    申请日：1998-02-24

    申请人： Hiroaki Sudo ,  Katsuhiko Hiramatsu ,  Mitsuru Uesugi

    发明人： Hiroaki Sudo ,  Katsuhiko Hiramatsu ,  Mitsuru Uesugi

    IPC分类号： H04L1/00 ,  H04B1/10 ,  H04J11/00 ,  H04L1/20 ,  H04L27/20

    CPC分类号： H04L1/206

    摘要： An estimator of error rate is provided for reducing variations of an error pulse count value at burst signals of a received signal for digital mobile communications and thereby improving an accuracy of estimating an error rate. The estimator of error rate includes detectors for detecting that phase information derived from a baseband signal of an I channel (I signal) and a baseband signal of a Q channel (Q signal) is located in an error pulse generation area, detectors for detecting that envelope information of the I signal and the Q signal is located in the error pulse generation area, and a counter for detecting that the phase error signal and the envelope error signal are outputted and counting the signals. The estimator operates to estimate an error rate based on an error pulse count value at one period. The estimator operates to detect that the phase information and the envelope information are located in the error pulse generation area. This serves to suppress the probability of counting correct signals and reducing variations of a count value at the burst signals, thereby improving an accuracy of estimating an error rate.

    摘要翻译： 提供误差率的估计器，用于减少用于数字移动通信的接收信号的脉冲串信号的误差脉冲计数值的变化，从而提高误差率的估计精度。 误差率的估计器包括用于检测从I信道（I信号）的基带信号和Q信道（Q信号）的基带信号导出的相位信息位于误差脉冲产生区域中的检测器，用于检测 I信号和Q信号的包络信息位于误差脉冲产生区域中，并且用于检测相位误差信号和包络误差信号的计数器，并对该信号进行计数。 估计器用于基于一个周期的错误脉冲计数值来估计错误率。 估计器操作以检测相位信息和包络信息位于错误脉冲产生区域中。 这用于抑制对正确信号进行计数并减少脉冲串信号处的计数值的变化的概率，从而提高误差率的估计精度。