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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100237346A1

    公开(公告)日：2010-09-23

    申请号：US12556102

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Mitsuru Sato

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Mitsuru Sato

    IPC分类号： H01L29/12 ,  H01L21/8246

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675

    摘要： A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer.The semiconductor layer and the third electrode layer are formed as follows. First, a first layer made from amorphous silicon and including a p-type first semiconductor region and an n-type second semiconductor region is deposited. Next, a second layer made from a metal is deposited on an upper or lower layer of the first layer. The third electrode layer including a metal silicide as a material lattice-matched to polysilicon is formed by siliciding the second layer. Next, the first layer is crystallized. Subsequently, the semiconductor layer is formed by activating an impurity included in the first layer and restoring crystal imperfections included in the first layer.

    摘要翻译： 整流器通过形成第一电极层，半导体层和第二电极层而形成。 在第一电极层和半导体层之间或第二电极层和半导体层之间形成第三电极层。 半导体层和第三电极层如下形成。 首先，沉积由非晶硅制成并包括p型第一半导体区域和n型第二半导体区域的第一层。 接下来，将由金属制成的第二层沉积在第一层的上层或下层上。 通过硅化第二层来形成包括与多晶硅晶格匹配的材料的金属硅化物的第三电极层。 接下来，第一层结晶。 随后，通过激活包括在第一层中的杂质并恢复包括在第一层中的晶体缺陷来形成半导体层。

    Non-volatile semiconductor memory device including memory cells with a variable resistor
    4.
    发明授权
    Non-volatile semiconductor memory device including memory cells with a variable resistor 有权
    包括具有可变电阻器的存储单元的非易失性半导体存储器件

    公开(公告)号：US08391048B2

    公开(公告)日：2013-03-05

    申请号：US12846198

    申请日：2010-07-29

    申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

    发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0061 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

    摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

    摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

    Nonvolatile semiconductor memory device
    5.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08320157B2

    公开(公告)日：2012-11-27

    申请号：US12876637

    申请日：2010-09-07

    申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Kenichi Murooka

    发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Kenichi Murooka

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/13 ,  G11C2213/34 ,  G11C2213/72

    摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.

    摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和 串联连接的可变电阻元件。 控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。 控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。

    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08084830B2

    公开(公告)日：2011-12-27

    申请号：US12556005

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    IPC分类号： H01L27/11

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1027

    摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0

    摘要翻译： 存储单元位于第一布线和第二布线之间的相应交点处。 每个存储单元具有串联连接的整流元件和可变电阻元件。 整流元件包括p型第一半导体区域和n型第二半导体区域。 第一半导体区域至少部分地由硅 - 锗混合物（Si1-xGex（0

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    7.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20110103128A1

    公开(公告)日：2011-05-05

    申请号：US12882685

    申请日：2010-09-15

    申请人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

    发明人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/02 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

    摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

    摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

    Storage device
    8.
    发明授权
    Storage device 有权
    储存设备

    公开(公告)号：US08766225B2

    公开(公告)日：2014-07-01

    申请号：US13040764

    申请日：2011-03-04

    申请人： Kenichi Murooka ,  Hiroshi Kanno

    发明人： Kenichi Murooka ,  Hiroshi Kanno

    IPC分类号： H01L29/02

    CPC分类号： H01L27/1021 ,  H01L27/101

    摘要： According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.

    摘要翻译： 根据实施例，存储装置包括彼此平行布置的行线，彼此平行布置以与行线相交的列线，以及设置在行线和列线的每个交叉处的存储单元，并且包括 与电阻变化元件串联连接的电阻变化元件和二极管。 二极管包括一个包含第一导电类型的杂质的第一半导体区的堆叠，含有比第一半导体区低的浓度的第一导电类型的杂质的第二半导体区和含有杂质的第三半导体区 第二导电类型。 与第一半导体区域相邻的第一相邻部分中的二极管的第二半导体区域中的杂质浓度高于与第三半导体区域相邻的第二相邻部分中的杂质浓度。

    Resistance change type memory
    9.
    发明授权
    Resistance change type memory 有权
    电阻变化型存储器

    公开(公告)号：US08324606B2

    公开(公告)日：2012-12-04

    申请号：US12563470

    申请日：2009-09-21

    申请人： Takayuki Tsukamoto ,  Reika Ichihara ,  Hiroshi Kanno ,  Kenichi Murooka

    发明人： Takayuki Tsukamoto ,  Reika Ichihara ,  Hiroshi Kanno ,  Kenichi Murooka

    IPC分类号： H01L47/00

    CPC分类号： G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481

    摘要： A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.

    摘要翻译： 本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端 布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件， 能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线 接线。

    Nonvolatile semiconductor memory device
    10.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08320158B2

    公开(公告)日：2012-11-27

    申请号：US12882685

    申请日：2010-09-15

    申请人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

    发明人： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

    IPC分类号： G11C11/00

    CPC分类号： G11C7/02 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

    摘要： Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

    摘要翻译： 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。