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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100237346A1

    公开(公告)日：2010-09-23

    申请号：US12556102

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Mitsuru Sato

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Mitsuru Sato

    IPC分类号： H01L29/12 ,  H01L21/8246

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675

    摘要： A rectifier is formed by forming a first electrode layer, a semiconductor layer and a second electrode layer. A third electrode layer is formed between the first electrode layer and the semiconductor layer, or between the second electrode layer and the semiconductor layer.The semiconductor layer and the third electrode layer are formed as follows. First, a first layer made from amorphous silicon and including a p-type first semiconductor region and an n-type second semiconductor region is deposited. Next, a second layer made from a metal is deposited on an upper or lower layer of the first layer. The third electrode layer including a metal silicide as a material lattice-matched to polysilicon is formed by siliciding the second layer. Next, the first layer is crystallized. Subsequently, the semiconductor layer is formed by activating an impurity included in the first layer and restoring crystal imperfections included in the first layer.

    摘要翻译： 整流器通过形成第一电极层，半导体层和第二电极层而形成。 在第一电极层和半导体层之间或第二电极层和半导体层之间形成第三电极层。 半导体层和第三电极层如下形成。 首先，沉积由非晶硅制成并包括p型第一半导体区域和n型第二半导体区域的第一层。 接下来，将由金属制成的第二层沉积在第一层的上层或下层上。 通过硅化第二层来形成包括与多晶硅晶格匹配的材料的金属硅化物的第三电极层。 接下来，第一层结晶。 随后，通过激活包括在第一层中的杂质并恢复包括在第一层中的晶体缺陷来形成半导体层。

    Nonvolatile memory device and method for driving same
    5.
    发明授权
    Nonvolatile memory device and method for driving same 失效
    非易失存储器件及其驱动方法

    公开(公告)号：US08274822B2

    公开(公告)日：2012-09-25

    申请号：US13018757

    申请日：2011-02-01

    申请人： Takayuki Tsukamoto ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

    发明人： Takayuki Tsukamoto ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

    IPC分类号： G11C11/00

    CPC分类号： H01L45/04 ,  G11C5/147 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72 ,  H01L45/145

    摘要： According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.

    摘要翻译： 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。

    NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME 失效
    非易失性存储器件及其驱动方法

    公开(公告)号：US20110286260A1

    公开(公告)日：2011-11-24

    申请号：US13018757

    申请日：2011-02-01

    申请人： Takayuki TSUKAMOTO ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

    发明人： Takayuki TSUKAMOTO ,  Yoichi Minemura ,  Natsuki Kikuchi ,  Mitsuru Sato ,  Hiroshi Kanno ,  Takafumi Shimotori

    IPC分类号： G11C11/00 ,  H01L45/00

    CPC分类号： H01L45/04 ,  G11C5/147 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/72 ,  H01L45/145

    摘要： According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.

    摘要翻译： 根据一个实施例，非易失性存储器件包括存储器单元和控制单元。 存储单元包括第一和第二互连以及存储单元。 第二互连与第一互连不平行。 存储单元包括设置在第一和第二互连之间的交叉点处的电阻变化层。 控制单元连接到第一和第二互连以向电阻变化层提供电压和电流。 控制单元在将电阻变化层从第一状态变化的设定动作中，基于第一配线的电位的变化来增大提供给第一配线的电流的上限， 具有第一电阻值到第二状态，其中第二电阻值小于第一电阻值。

    Nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08675388B2

    公开(公告)日：2014-03-18

    申请号：US13233679

    申请日：2011-09-15

    申请人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

    发明人： Yoichi Minemura ,  Takayuki Tsukamoto ,  Takafumi Shimotori ,  Hiroshi Kanno ,  Natsuki Kikuchi ,  Mitsuru Sato

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0083 ,  G11C2213/71

    摘要： A nonvolatile semiconductor memory device includes: a memory cell array including plural first lines, plural second lines, and plural memory cells each including a variable resistance element; a first decoder connected to at least one ends of the plurality of first lines and configured to select at least one of the first lines; at least one pair of second decoders connected to both ends of the plurality of second lines and configured such that one of the pair of second decoders is selected for selecting the second lines according to a distance between the one of the first lines selected by the first decoder and the both ends of the second lines; and a voltage application circuit configured to apply a certain voltage between the first line and the second line selected by the first decoder and the second decoder.

    摘要翻译： 非易失性半导体存储器件包括：包括多个第一线，多个第二线和多个存储单元的存储单元阵列，每个存储单元包括可变电阻元件; 第一解码器，连接到所述多条第一线的至少一端，并被配置为选择所述第一线中的至少一条线; 至少一对第二解码器，连接到所述多个第二线路的两端，并且被配置为使得所述一对第二解码器中的一个被选择用于根据所述第一线选择的所述第一线之间的距离来选择所述第二线 解码器和第二行的两端; 以及电压施加电路，被配置为在由第一解码器和第二解码器选择的第一线和第二线之间施加一定电压。

    Method for manufacturing semiconductor device and semiconductor device
    8.
    发明授权
    Method for manufacturing semiconductor device and semiconductor device 有权
    半导体器件和半导体器件的制造方法

    公开(公告)号：US09076820B2

    公开(公告)日：2015-07-07

    申请号：US13600373

    申请日：2012-08-31

    申请人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

    发明人： Soichiro Kitazaki ,  Masaru Kidoh ,  Mitsuru Sato ,  Ryota Katsumata ,  Tadashi Iguchi

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66666 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/7827

    摘要： According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

    摘要翻译： 根据一个实施例，一种用于制造半导体器件的方法包括形成多个绝缘隔离部分，其被设置为沿第一方向延伸，使堆叠体沿第二方向隔离，并具有从堆叠体突出的突出部。 每个绝缘隔离部分具有侧壁，该侧壁包括沿着第一方向重复的凹陷部分和突出部分。 该方法包括在绝缘隔离部分的突起的侧壁上形成侧壁膜，并且在多个绝缘隔离部分之间形成由侧壁膜围绕并由第一方向隔离的多个第一孔 。 该方法包括通过用绝缘隔离部分和用作掩模的侧壁膜进行蚀刻，在设置在第一孔下方的层叠体中形成第二孔。

    Input/output connection device, information processing device, and method for inspecting input/output device
    9.
    发明授权
    Input/output connection device, information processing device, and method for inspecting input/output device 有权
    输入/输出连接装置，信息处理装置和检测输入/输出装置的方法

    公开(公告)号：US08867369B2

    公开(公告)日：2014-10-21

    申请号：US13047137

    申请日：2011-03-14

    申请人： Mitsuru Sato

    发明人： Mitsuru Sato

    IPC分类号： H04L12/26 ,  G06F13/42 ,  G06F13/20 ,  G06F3/00

    CPC分类号： G06F13/4295

    摘要： An input/output connection device includes a generating section which generates an inspection packet that has a tag that uniquely identifies the packet, a transmitting section which transmits the inspection packet to the input/output device, a receiving section which receives a packet, a first determining section which determines, on the basis of a tag of the packet received by the receiving section, whether or not the received packet is a packet transmitted in response to the inspection packet transmitted by the transmitting section, and a second determining section which analyzes the received packet and determines whether or not the input/output device is normal when the first determining section determines that the received packet is the packet transmitted in response to the inspection packet.

    摘要翻译： 一种输入/输出连接装置，包括：生成部，其生成具有唯一地识别分组的标签的检查分组;将检查分组发送到输入/输出装置的发送部;接收分组的接收部; 确定部，其基于由所述接收部接收到的分组的标签，确定所接收的分组是否是响应于由所述发送部发送的所述检查分组而发送的分组;以及第二确定部， 并且当第一确定部确定接收到的分组是响应于检查分组而发送的分组时，确定输入/输出设备是否正常。

    Solid-state imaging device
    10.
    发明授权
    Solid-state imaging device 有权
    固态成像装置

    公开(公告)号：US08598640B2

    公开(公告)日：2013-12-03

    申请号：US13211362

    申请日：2011-08-17

    申请人： Yoshiaki Kitano ,  Hideshi Abe ,  Jun Kuroiwa ,  Kiyoshi Hirata ,  Hiroaki Ohki ,  Nobuhiro Karasawa ,  Ritsuo Takizawa ,  Mitsuru Yamashita ,  Mitsuru Sato ,  Katsunori Kokubun

    发明人： Yoshiaki Kitano ,  Hideshi Abe ,  Jun Kuroiwa ,  Kiyoshi Hirata ,  Hiroaki Ohki ,  Nobuhiro Karasawa ,  Ritsuo Takizawa ,  Mitsuru Yamashita ,  Mitsuru Sato ,  Katsunori Kokubun

    IPC分类号： H01L31/113 ,  H01L27/146

    CPC分类号： H01L27/14601 ,  H01L27/14689 ,  H01L27/14806 ,  H04N5/335

    摘要： A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area is formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area is formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area.

    摘要翻译： 具有这样一种结构的固态成像装置，该结构使得用于读取信号电荷的电极设置在构成像素的光接收传感器部分的一侧; 将预定的电压信号V施加到形成为覆盖除了光接收传感器部分之外的图像拾取区域的遮光膜; 第二导电型半导体区域形成在构成光接收传感器部分的光电转换区域的第一导电型半导体区域的表面上的中心; 并且在第一导电型半导体区域的电极侧的端部的表面上形成比第二导电型半导体区域的杂质浓度低的区域， 像素分离区域。