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19 条记录 (耗时 0.03 秒)

    Nonvolatile semiconductor memory device
    1.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08084830B2

    公开(公告)日：2011-12-27

    申请号：US12556005

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    IPC分类号： H01L27/11

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1027

    摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0

    摘要翻译： 存储单元位于第一布线和第二布线之间的相应交点处。 每个存储单元具有串联连接的整流元件和可变电阻元件。 整流元件包括p型第一半导体区域和n型第二半导体区域。 第一半导体区域至少部分地由硅 - 锗混合物（Si1-xGex（0

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20100213550A1

    公开(公告)日：2010-08-26

    申请号：US12556005

    申请日：2009-09-09

    申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

    IPC分类号： H01L27/10

    CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1027

    摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Sii-xGex (0

    摘要翻译： 存储单元位于第一布线和第二布线之间的相应交点处。 每个存储单元具有串联连接的整流元件和可变电阻元件。 整流元件包括p型第一半导体区域和n型第二半导体区域。 第一半导体区域至少部分地由硅 - 锗混合物（Sii-xGex（0

    Process for producing conjugated diolefinic polymers
    4.
    发明授权
    Process for producing conjugated diolefinic polymers 失效
    制备共轭二烯聚合物的方法

    公开(公告)号：US4097661A

    公开(公告)日：1978-06-27

    申请号：US788351

    申请日：1977-04-18

    申请人： Koei Komatsu ,  Kenji Itoyama ,  Jun Hirota ,  Akio Nishijima

    发明人： Koei Komatsu ,  Kenji Itoyama ,  Jun Hirota ,  Akio Nishijima

    IPC分类号： C08F4/00 ,  C08F2/38 ,  C08F4/42 ,  C08F4/46 ,  C08F36/00 ,  C08F36/04 ,  C08F4/56

    CPC分类号： C08F36/04

    摘要： A process for producing a conjugated diolefinic polymer by polymerizing at least one conjugated diolefin or copolymerizing at least one conjugated diolefin with at least one vinyl aromatic hydrocarbon in a hydrocarbon solvent in the presence of an alfin catalyst and at least one molecular weight regulator selected from the group consisting of (A) unsaturated halohydrocarbons represented by the general formula, RCX .dbd. CYZ, wherein R represents hydrogen, an alkyl group having 1 to 7 carbon atoms, a vinyl group, a phenyl group, a substituted phenyl group, or a halogen atom and X, Y and Z represent independently a hydrogen or halogen atom, at least one of said R, X, Y and Z being a halogen atom, (B) halogenated aromatic hydrocarbons, (C) ethers, polyethers, and acetals and (D) tertiary amines and, if necessary, a dihydro aromatic hydrocarbon, characterized in that said polymerization or copolymerization is effected in the presence of 0.03 to 0.9 mole of water and/or an alcohol per mole of organosodium contained in said alfin catalyst. According to this invention, there is obtained a polymer or copolymer excellent in green strength and processability of the unvulcanized compound and in physical properties of the vulcanizate.

    摘要翻译： 一种制备共轭二烯烃聚合物的方法，其通过在烯烃催化剂和至少一种分子量调节剂的存在下，在烃溶剂中聚合至少一种共轭二烯烃或共聚至少一种共轭二烯烃与至少一种乙烯基芳烃， 由以下通式表示的（A）不饱和卤代烃：RCX = CYZ，其中R表示氢，具有1至7个碳原子的烷基，乙烯基，苯基，取代的苯基或卤素原子 并且X，Y和Z分别独立地表示氢原子或卤素原子，所述R，X，Y和Z中的至少一个为卤素原子，（B）卤代芳香烃，（C）醚，聚醚和缩醛和（D ）叔胺和如果需要的二氢芳族烃，其特征在于所述聚合或共聚在每摩尔o的0.03至0.9摩尔的水和/或醇的存在下进行 所述烯烃催化剂中含有的果糖钠。 根据本发明，获得了未硫化化合物的生坯强度和加工性能以及硫化橡胶的物理性能优异的聚合物或共聚物。

    Memory device and method for manufacturing same
    5.
    发明授权
    Memory device and method for manufacturing same 失效
    存储器件及其制造方法

    公开(公告)号：US08436331B2

    公开(公告)日：2013-05-07

    申请号：US12844374

    申请日：2010-07-27

    申请人： Yoko Iwakaji ,  Jun Hirota ,  Kyoichi Suguro ,  Moto Yabuki

    发明人： Yoko Iwakaji ,  Jun Hirota ,  Kyoichi Suguro ,  Moto Yabuki

    IPC分类号： H01L21/02

    CPC分类号： H01L27/1021 ,  G11C13/0007 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1675

    摘要： According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.

    摘要翻译： 根据一个实施例，公开了一种用于制造存储器件的方法。 该方法包括形成硅二极管。 至少硅二极管的上部由含有硅并掺杂杂质的半导体材料制成。 该方法包括在硅二极管上形成由金属制成的金属层。 该方法包括在金属层上形成由金属的氮化物制成的金属氮化物层。 该方法包括形成电阻变化膜。 此外，该方法包括通过热处理使金属层与硅二极管和金属氮化物层反应，以形成含有金属，硅和氮的电极膜。

    Communication terminal device, information providing device, and cellular telephone system
    6.
    发明申请
    Communication terminal device, information providing device, and cellular telephone system 有权
    通信终端设备，信息提供设备和蜂窝电话系统

    公开(公告)号：US20050256966A1

    公开(公告)日：2005-11-17

    申请号：US11118380

    申请日：2005-05-02

    申请人： Jun Hirota ,  Masaki Kinoshita

    发明人： Jun Hirota ,  Masaki Kinoshita

    IPC分类号： H04M3/42 ,  G06F3/14 ,  H04L29/06 ,  H04M1/02 ,  H04M1/725 ,  H04M3/493 ,  H04M11/08 ,  H04Q7/38 ,  G06F15/16

    CPC分类号： H04L65/604 ,  H04L29/06027 ,  H04L65/4092 ,  H04L65/608 ,  H04M1/0214 ,  H04M2250/16 ,  H04N21/2543 ,  H04N21/41407 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/4882 ,  H04N21/6581 ,  H04N21/8133

    摘要： A communication terminal device includes a first display part configured to display streaming sub information, a second display part configured to display streaming main information related to the streaming sub information, a sub information reception unit configured to receive the streaming sub information sequentially transmitted from an information providing device and to display the received streaming sub information on the first display part, a request transmission unit configured to transmit to the information providing device an information request signal for requesting the streaming main information related to the streaming sub information displayed on the first display part, and a main information reception unit configured to receive the streaming main information and to display the streaming main information on the second display part.

    摘要翻译： 一种通信终端装置，具备：第一显示部，被配置为显示流媒体子信息;第二显示部，被配置为显示与所述流媒体子信息相关的流媒体主信息;子信息接收部，被配置为接收从信息顺序发送的流式传输子信息 提供设备并在第一显示部分上显示所接收的流式传输子信息;请求传输单元，被配置为向信息提供设备发送信息请求信号，用于请求与第一显示部分上显示的流式传输子信息相关的传输主要信息 以及主信息接收单元，被配置为接收流式主信息并在第二显示部分上显示流主要信息。

    Semiconductor memory device and method of manufacturing same
    7.
    发明授权
    Semiconductor memory device and method of manufacturing same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US08309958B2

    公开(公告)日：2012-11-13

    申请号：US12872284

    申请日：2010-08-31

    申请人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

    发明人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

    IPC分类号： H01L29/06 ,  H01L29/12 ,  H01L45/00

    CPC分类号： H01L27/1021 ,  H01L27/101

    摘要： According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.

    摘要翻译： 根据一个实施例，半导体存储器件包括字线互连层，位线互连层和柱。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向交叉的第二方向延伸的多个位线。 支柱布置在每个字线和每个位线之间。 支柱包括硅二极管和可变电阻膜，并且硅二极管包括p型部分和n型部分。 字线互连层和位线互连层交替堆叠，并且在p型部分和n型部分变得更接近的方向上对硅二极管施加压缩力。

    NONVOLATILE MEMORY DEVICE
    10.
    发明申请
    NONVOLATILE MEMORY DEVICE 失效
    非易失性存储器件

    公开(公告)号：US20120235107A1

    公开(公告)日：2012-09-20

    申请号：US13236713

    申请日：2011-09-20

    申请人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

    发明人： Jun Hirota ,  Yoko Iwakaji ,  Moto Yabuki

    IPC分类号： H01L45/00

    CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/1675

    摘要： According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.

    摘要翻译： 根据一个实施例，非易失性存储器件包括字线互连层，位线互连层，柱和电荷承载部件。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿与第一方向相交的第二方向延伸的多个位线。 支柱设置在每个字线和每个位线之间。 电荷承载部件包含负的固定电荷，并且设置在支柱的侧面上。 支柱包括二极管膜，该二极管膜设置有层叠在二极管膜上的p型层和n型层以及可变电阻膜。 电荷承载部件配置在p型层的侧面，不配置在n型层的侧面。