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公开(公告)号:US4947388A
公开(公告)日:1990-08-07
申请号:US333282
申请日:1989-04-05
申请人: Hiroshi Kuwahara , Mineo Ogino , Takahiko Kozaki , Noboru Endo , Yoshito Sakurai
发明人: Hiroshi Kuwahara , Mineo Ogino , Takahiko Kozaki , Noboru Endo , Yoshito Sakurai
IPC分类号: H04Q3/00 , H04L12/931
CPC分类号: H04L12/5601 , H04L49/108 , H04L49/203
摘要: A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions. The system includes a buffer memory having a first buffer area composed of a plurality of subsidiary areas for accumulating cells correspondingly to the output lines, and a second buffer area for accumulating broadcast cells to be transmitted to selected ones of the plurality of output lines; a packet reading circuit for reading the cells from the first buffer area successively corresponding to the output lines and for reading the broadcast cell from the second buffer area at a predetermined frequency; and a broadcast control circuit for reproducing a plurality of broadcast cells from the broadcast cells read from the second buffer area and for transmitting the plurality of reproduced broadcast cells, instead of the cells read from the first buffer area, onto the output lines. The buffer memory is divided into a plurality of buffer areas each corresponding to a respective output line and a packet writing circuit generates addresses sequentially for the respective buffer areas to store cells in a buffer area according to the header portion thereof.
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公开(公告)号:US4964119A
公开(公告)日:1990-10-16
申请号:US334211
申请日:1989-04-06
IPC分类号: H04L12/801 , H04L12/931
CPC分类号: H04L49/103 , H04L49/25 , H04L49/254 , H04L49/30 , H04L49/3009
摘要: In a packet exchange system for preforming packet exchange by setting logical channels, individual input packets are assigned with information indicative of input sequence of the individual input packets counted in each call and the input sequence information is stored. Each time each packet is delivered, the input sequence information assigned to an input packet is stored as an output sequence information in a call to which the delivered packet belongs, and the status of congestion of packets of the call which are present in the exchange is decided on the basis of the stored input sequence information and output sequence information. This system further includes a rerouting circuit having buffer function and a control device for changing the contents of a conversion table when it detects by looking up the conversion table that the number of packets remaining in the exchange which are destined for a specified output line exceeds a predetermined threshold, whereby input packets scheduled to be destined for the specified output line are temporarily stored in the rerouting circuit.
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公开(公告)号:US06314096B1
公开(公告)日:2001-11-06
申请号:US09467213
申请日:1999-12-20
申请人: Shirou Tanabe , Taihei Suzuki , Shinobu Gohara , Yoshito Sakurai , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人: Shirou Tanabe , Taihei Suzuki , Shinobu Gohara , Yoshito Sakurai , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号: H04L1228
CPC分类号: H04Q11/0421 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/1507 , H04L49/1553 , H04L49/1584 , H04L49/25 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L2012/563 , H04L2012/5632 , H04L2012/5652 , H04L2012/5671 , H04L2012/5672 , H04L2012/568 , H04L2012/6481 , H04Q11/0407 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13141 , H04Q2213/13176 , H04Q2213/13204 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13332 , H04Q2213/13352 , H04Q2213/13399
摘要: In a packet switching system made up of a single or a plurality of switching nodes or local units each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch on the basis of a logic channel on a packet circuit, a self-routing switch for performing switching on the basis of the output port information, land a control unit for terminating a control packet and performing the call processing function, and a switching node or tandem unit including a single or a plurality of self-routing switches for interconnecting the local units, there are provided a device for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating-side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device, operable in the originating side local unit for information transfer, for inserting output port information of the self-routing switch inside the tandem unit into a packet destined for the local unit other than this local unit, whereby in the tandem unit, setting of logic channel conversion information is not required to be done and even when any control signal packet from the originating-side local unit arrives at the tandem unit, the packet is transferred to the destination-side local unit without undergoing termination of packet and concomitant call processing control.
摘要翻译: 在由单个或多个交换节点或本地单元组成的分组交换系统中,每个交换节点或本地单元包括用于容纳多个分组电路的标签转换单元,并且基于逻辑信道对交换机的输出端口信息进行转换 分组电路,用于基于输出端口信息进行切换的自路由交换机,用于终止控制分组并执行呼叫处理功能的控制单元,以及包括单个或多个的交换节点或串联单元 的用于互连本地单元的自路由交换机,提供了一种用于在串联单元和目的地侧本地单元之间设置与用于信息传输的始发侧本地单元和与目的地侧本地单元相同的逻辑信道的设备, 关于发往本地单元以外的本地单元的呼叫的串联单元和可在始发方本地单元中操作的设备的装置 传输,用于将串联单元内的自路由交换机的输出端口信息插入目的地为本地单元以外的本地单元的分组,由此在串联单元中,不需要设置逻辑信道转换信息, 即使当来自始发方本地单元的任何控制信号分组到达串联单元时,分组被传送到目的地侧本地单元,而不会发生分组的终止和伴随的呼叫处理控制。
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公开(公告)号:US06285675B1
公开(公告)日:2001-09-04
申请号:US09228748
申请日:1999-01-12
申请人: Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
发明人: Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
IPC分类号: H04L1256
CPC分类号: H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682 , H04Q11/0478
摘要: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
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公开(公告)号:US5995510A
公开(公告)日:1999-11-30
申请号:US903176
申请日:1997-07-30
申请人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号: H04L12/54 , H04L12/64 , H04L12/70 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L12/947 , H04Q11/04 , H04Q11/06
CPC分类号: H04L49/30 , H04L12/56 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/15 , H04L49/1553 , H04L49/1584 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/35 , H04Q11/0407 , H04Q11/0421 , H04Q11/06 , H04J2203/0012 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681 , H04L2012/6481 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3009 , H04L49/3018
摘要: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.
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公开(公告)号:US5513177A
公开(公告)日:1996-04-30
申请号:US654590
申请日:1991-02-13
申请人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号: H04L12/54 , H04L12/64 , H04L12/70 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L12/947 , H04Q11/04 , H04Q11/06
CPC分类号: H04L49/30 , H04L12/56 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/15 , H04L49/1553 , H04L49/1584 , H04L49/255 , H04L49/256 , H04L49/3081 , H04L49/309 , H04L49/35 , H04Q11/0407 , H04Q11/0421 , H04Q11/06 , H04J2203/0012 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681 , H04L2012/6481 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/3009 , H04L49/3018
摘要: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.
摘要翻译: 一种用于集成地切换语音,数据,图像信息等的切换系统。 交换系统包括多个前端模块,每个前端模块适于与用户线路或中继线路相关联地执行切换处理;以及单个或多个中央模块,用于以星形模式互连多个前端模块, 在前端模块之间存在的类型时尚和切换信息,以容纳信息的块为单位,以及添加到其中的标题,以包含连接控制信息并根据报头的内容。 前端模块通过模块间高速公路连接到中央模块,每个模块高速公路都具有以预定周期发生的帧,并且包含在每个帧中的时隙以承载块。
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公开(公告)号:US06639920B2
公开(公告)日:2003-10-28
申请号:US10102912
申请日:2002-03-22
申请人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号: H04J326
CPC分类号: H04L49/30 , H04J2203/0012 , H04L12/56 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/15 , H04L49/1553 , H04L49/1584 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/3009 , H04L49/3018 , H04L49/3081 , H04L49/309 , H04L49/35 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681 , H04L2012/6481 , H04Q11/0407 , H04Q11/0421 , H04Q11/06
摘要: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.
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公开(公告)号:US06618372B1
公开(公告)日:2003-09-09
申请号:US09340139
申请日:1999-06-28
申请人: Shirou Tanabe , Taihei Suzuki , Shinobu Gohara , Yoshito Sakurai , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人: Shirou Tanabe , Taihei Suzuki , Shinobu Gohara , Yoshito Sakurai , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号: H04L1256
CPC分类号: H04Q11/0421 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/1507 , H04L49/1553 , H04L49/1584 , H04L49/25 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/30 , H04L49/3009 , H04L49/3081 , H04L49/309 , H04L2012/563 , H04L2012/5632 , H04L2012/5652 , H04L2012/5671 , H04L2012/5672 , H04L2012/568 , H04L2012/6481 , H04Q11/0407 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13141 , H04Q2213/13176 , H04Q2213/13204 , H04Q2213/13209 , H04Q2213/13216 , H04Q2213/1329 , H04Q2213/13292 , H04Q2213/13332 , H04Q2213/13352 , H04Q2213/13399
摘要: In a packet switching system-made up of a single or a plurality of switching nodes or local units each including a label conversion unit for accommodating a plurality of packet circuits and performing conversion into output port information of a switch on the basis of a logic channel on a packet circuit, a self-routing switch for performing switching on the basis of the output port information, and a control unit for terminating a control packet and performing the call processing function, and a switching node or tandem unit including a single or a plurality of self-routing switches for interconnecting the local units, there are provided a device for setting, between the tandem unit and a destination-side local unit, the same logic channel as that between an originating, side local unit operative for information transfer and the tandem unit in respect of a call destined for a local unit other than this local unit and a device, operable in the originating-side local unit for information transfer, for inserting output port information of the self-routing switch inside the tandem unit into a packet destined for the local unit other than this local unit, whereby in the tandem unit, setting of logic channel conversion information is not required to be done and even when any control signal packet from the originating side local unit arrives at the tandem unit, the packet is transferred to the destination side local unit without undergoing termination of packet and concomitant call processing control.
摘要翻译: 在由单个或多个交换节点或本地单元组成的分组交换系统中,每个交换节点或本地单元包括用于容纳多个分组电路的标签转换单元,并且基于逻辑信道对转换器的输出端口信息进行转换 在分组电路上,基于输出端口信息执行切换的自路由交换机,以及用于终止控制分组并执行呼叫处理功能的控制单元,以及包括单个或一个或多个的交换节点或串联单元 多个用于互连本地单元的自路由交换机,提供了一种用于在串联单元和目的地侧本地单元之间设置与用于信息传输的始发侧本地单元和用于信息传输的本地单元之间相同的逻辑信道的设备, 关于发往本地本地单元以外的本地单元的呼叫的串联单元和可在始发方本地单元中操作的设备的装置 传输,用于将串联单元内的自路由交换机的输出端口信息插入目的地为本地单元以外的本地单元的分组,由此在串联单元中,不需要设置逻辑信道转换信息, 即使当来自始发方本地单元的任何控制信号分组到达串联单元时,分组被传送到目的地侧本地单元,而不会发生分组的终止和伴随的呼叫处理控制。
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公开(公告)号:US06389025B2
公开(公告)日:2002-05-14
申请号:US09873280
申请日:2001-06-05
申请人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
发明人: Yoshito Sakurai , Shinobu Gohara , Kenichi Ohtsuki , Takao Kato , Hiroshi Kuwahara , Eiichi Amada
IPC分类号: H04J326
CPC分类号: H04L49/30 , H04J2203/0012 , H04L12/56 , H04L12/5601 , H04L12/6402 , H04L49/101 , H04L49/106 , H04L49/15 , H04L49/1553 , H04L49/1584 , H04L49/205 , H04L49/25 , H04L49/254 , H04L49/255 , H04L49/256 , H04L49/3009 , H04L49/3018 , H04L49/3081 , H04L49/309 , H04L49/35 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681 , H04L2012/6481 , H04Q11/0407 , H04Q11/0421 , H04Q11/06
摘要: A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetrmined period and time slots contained in each frame to carry blocks.
摘要翻译: 一种用于集成地切换语音,数据,图像信息等的切换系统。 交换系统包括多个前端模块,每个前端模块适于与用户线路或中继线路相关联地执行切换处理;以及单个或多个中央模块,用于以星形模式互连多个前端模块, 在前端模块之间存在的类型时尚和切换信息,以容纳信息的块为单位,以及添加到其中的标题,以包含连接控制信息并根据报头的内容。 前端模块通过模块间高速公路连接到中央模块,每个模块都具有在预定周期内发生的帧,并且包含在每个帧中的时隙以承载块。
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公开(公告)号:US6016317A
公开(公告)日:2000-01-18
申请号:US462269
申请日:1995-06-05
申请人: Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
发明人: Yoshito Sakurai , Kenichi Ohtsuki , Shinobu Gohara , Makoto Mori , Akira Horiki , Takao Kato , Hiroshi Kuwahara
CPC分类号: H04L12/5601 , H04J3/247 , H04L12/5602 , H04L45/04 , H04L49/108 , H04L49/203 , H04L49/255 , H04L49/256 , H04L49/3081 , H04Q11/0478 , H04L2012/5627 , H04L2012/5631 , H04L2012/5638 , H04L2012/5649 , H04L2012/565 , H04L2012/5651 , H04L2012/5652 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04L2012/5681 , H04L2012/5682
摘要: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.
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