公开(公告)号：US06288921B1

公开(公告)日：2001-09-11

申请号：US09639882

申请日：2000-08-17

申请人： Hiroshi Uchino ,  Ryuichi Morikawa ,  Kiyoshi Kusunoki ,  Takeo Kanai ,  Tadashi Nishikawa

发明人： Hiroshi Uchino ,  Ryuichi Morikawa ,  Kiyoshi Kusunoki ,  Takeo Kanai ,  Tadashi Nishikawa

IPC分类号： H02M75387

CPC分类号： H02M7/487 ,  H02M7/527 ,  H02M2007/53876

摘要： A control apparatus for a power converter having a plurality of semiconductor switching devices that converts DC power into AC power and outputs three levels of voltages, including a command voltage generator configured to output a command voltage vector that represents a voltage to be output from the power converter, an integrator configured to calculate a difference integral vector by integrating a difference between the command voltage vector and an output voltage vector that represents a voltage command for the power converter, a difference vector calculator configured to calculate difference vectors by subtracting the command voltage vector from each of the possible output voltage vectors, a vector selector configured to select one of the possible output voltage vectors which corresponds to one of the difference vectors making the largest angle with the difference integral vector as the output voltage vector only if the difference integral vector exceeds a predetermined value, and a gate signal generator configured to determine one of switching states that includes a plurality of ON-OFF pattern signals for turning on and off the semiconductor switching devices on the basis of the output voltage vector.

摘要翻译： 一种用于功率转换器的控制装置，具有多个半导体开关器件，其将DC电力转换为AC电力并输出三个电压电平，包括命令电压发生器，其被配置为输出表示从功率输出的电压的指令电压矢量 转换器，积分器，被配置为通过积分指示电压矢量和表示电力转换器的电压指令的输出电压矢量之间的差来计算差分积分矢量;差分矢量计算器，被配置为通过减去指令电压矢量 从每个可能的输出电压矢量，矢量选择器被配置为选择一个可能的输出电压矢量，该输出电压矢量对应于与差积分矢量产生最大角度的一个差分矢量作为输出电压矢量，只有当差积分矢量 超过预定值， 门信号发生器，其被配置为基于输出电压矢量来确定包括用于接通和断开半导体开关器件的多个导通和截止图案信号的开关状态之一。

公开(公告)号：US5570260A

公开(公告)日：1996-10-29

申请号：US160847

申请日：1993-12-03

申请人： Takeo Kanai ,  Kiyoshi Kusunoki

发明人： Takeo Kanai ,  Kiyoshi Kusunoki

IPC分类号： H02H7/08 ,  H02H3/00 ,  H02H7/12 ,  H02H7/125 ,  H02H9/04 ,  H02M1/00 ,  H02M1/088 ,  H02M7/515 ,  H02P23/00 ,  H02H9/00

CPC分类号： H02M1/088 ,  H02H3/006 ,  H02H7/08 ,  H02H7/125

摘要： An overvoltage protection circuit including a plurality of series connected thyristors having an overvoltage protection function and a plurality of impedance circuits. Each of the impedance circuits is connected in parallel with one of the thyristors, respectively. The impedance circuits include at least a first impedance circuit having a first impedance value and a second impedance circuit having a second impedance value which is different from the first impedance value.

摘要翻译： 一种过电压保护电路，包括具有过电压保护功能的多个串联连接的晶闸管和多个阻抗电路。 每个阻抗电路分别与一个晶闸管并联连接。 阻抗电路至少包括具有第一阻抗值的第一阻抗电路和具有与第一阻抗值不同的第二阻抗值的第二阻抗电路。

公开(公告)号：US06169677A

公开(公告)日：2001-01-02

申请号：US09413872

申请日：1999-10-07

申请人： Takeshi Kitahata ,  Hiroyuki Nishikawa ,  Hiroshi Uchino ,  Takashi Fujita ,  Takahisa Kageyama ,  Takeo Kanai ,  Akira Kawaguchi ,  Tadahiro Sakamoto

发明人： Takeshi Kitahata ,  Hiroyuki Nishikawa ,  Hiroshi Uchino ,  Takashi Fujita ,  Takahisa Kageyama ,  Takeo Kanai ,  Akira Kawaguchi ,  Tadahiro Sakamoto

IPC分类号： H02M700

CPC分类号： H02M7/49 ,  H02M2007/53876

摘要： A power converting system has power converters for converting a direct current into an alternating current, a DC power source arranged on the DC side of the power converters, and voltage dividing transformers having windings whose first ends are connected to the power converters phase by phase and whose second ends are joined together and connected to a load phase by phase. Also provided is a controller for controlling the power converting system.

摘要翻译： 电力转换系统具有用于将直流电转换为交流电的电力转换器，布置在电力转换器的直流侧的直流电源和分压变压器，其分压变压器的第一端逐段连接到电力转换器， 其第二端连接在一起，并通过相位连接到负载相。 还提供了一种用于控制电力转换系统的控制器。

公开(公告)号：US07215179B2

公开(公告)日：2007-05-08

申请号：US10535102

申请日：2003-09-26

申请人： Takanori Yamazoe ,  Takeo Kanai

发明人： Takanori Yamazoe ,  Takeo Kanai

IPC分类号： G05F1/10

CPC分类号： G11C5/146 ,  G11C5/145 ,  H02M3/073 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/076

摘要： The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

摘要翻译： 本发明涉及一种非易失性存储器的升压电路，其需要等于或高于电源电压的正或负高电压。 本发明即使在等于或低于3V的低电源电压下也可产生大约12V的高电压，并且不仅通过相同电路产生正高电压而且产生负高电压。 此外，通过将根据本发明的升压电路的身体控制型并联电荷泵与串联型电荷泵组合，可以有效地产生两种类型的高电压，并且可以实现芯片面积的减少 。

公开(公告)号：US06271708B1

公开(公告)日：2001-08-07

申请号：US09368162

申请日：1999-08-05

申请人： Kimihiro Hoshi ,  Takeo Kanai

发明人： Kimihiro Hoshi ,  Takeo Kanai

IPC分类号： H03K1704

CPC分类号： H03K17/164 ,  H03K17/168 ,  H03K17/567

摘要： In a gate circuit having a turn-off gate circuit composed of: OFF gate power source Eoff of which one terminal is connected to the emitter of semiconductor switching element 81, and switch SWoff that connects the other terminal of OFF gate power source Eoff and the gate of semiconductor switching element S1 via resistor Rg, the gate circuit is provided with second switch SWoff2 that connects the other terminal of OFF gate power source Eoff and the gate of semiconductor switching element S1. By closing second switch SWoff2 at the timing at which the turn-off operation is completed, it will connect to OFF gate power source Eoff without passing through a resistor.

摘要翻译： 在具有截止门电路的门电路中，包括：一个端子连接到半导体开关元件81的发射极的OFF栅极电源Eoff和将OFF栅极电源Eoff的另一个端子和 通过电阻器Rg的半导体开关元件S1的栅极，栅极电路设置有连接关闭栅极电源Eoff的另一端子和半导体开关元件S1的栅极的第二开关SWoff2。 通过在关断操作完成的定时关闭第二开关SWoff2，它将连接到OFF栅极电源Eoff而不通过电阻器。

公开(公告)号：US5631378A

公开(公告)日：1997-05-20

申请号：US591022

申请日：1996-01-25

申请人： Yoshio Urawa ,  Akihiko Shimotani ,  Takeo Kanai ,  Masahiko Tsujii

发明人： Yoshio Urawa ,  Akihiko Shimotani ,  Takeo Kanai ,  Masahiko Tsujii

IPC分类号： C07D277/20 ,  C07D277/38 ,  C07D277/40 ,  C07D277/42 ,  C07D499/08 ,  C07D501/00 ,  C07D501/06 ,  C07D501/34

CPC分类号： C07D277/587 ,  C07D277/20 ,  C07D277/42 ,  C07D501/00 ,  Y02P20/55

摘要： Described is a protected aminothiazolylacetic acid derivative represented by the following formula (I): ##STR1## wherein A represents a nitrogen atom or a methine group, R.sup.1 and R.sup.2 may be the same or different and individually represent a hydrogen atom, a lower alkyl group or a substituted or unsubstituted aryl group, R.sup.3 represents a lower alkoxy group, a halogenated lower alkoxy group, a triphenylmethoxy group, a lower alkyl group or an acyloxy group, and R.sup.4 represents a halogen atom, a hydroxy group, a lower alkoxy group or a substituted or unsubstituted amino group; and salts thereof; as well as processes for the preparation thereof. The protected aminothaizolylacetic acid derivative according to the present invention is an useful intermediate for introducing a 2-(2-aminothiazol-4-yl)-2-alkoxyiminoacetyl group or a 2-(2-aminotiazol-4-yl)-2-alkenoyl group into a cephem skeleton.

公开(公告)号：US08050085B2

公开(公告)日：2011-11-01

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C7/10 ,  G11C11/40

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US20090213649A1

公开(公告)日：2009-08-27

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/14 ,  G06F12/14

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US07009890B2

公开(公告)日：2006-03-07

申请号：US10317087

申请日：2002-12-12

申请人： Takanori Yamazoe ,  Hiroshi Yoshigi ,  Takeo Kanai

发明人： Takanori Yamazoe ,  Hiroshi Yoshigi ,  Takeo Kanai

IPC分类号： G11C16/00

CPC分类号： G11C16/26 ,  G11C16/32

摘要： A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories. Moreover, the read timing of the reference memories is outputted as an external interface.

公开(公告)号：US4433142A

公开(公告)日：1984-02-21

申请号：US376214

申请日：1982-05-07

申请人： Keizo Takayanagi ,  Yasuhide Tanaka ,  Tasuke Kawabata ,  Fujio Nakamura ,  Yukio Morita ,  Shigeto Negi ,  Takeo Kanai ,  Eiichi Morita

发明人： Keizo Takayanagi ,  Yasuhide Tanaka ,  Tasuke Kawabata ,  Fujio Nakamura ,  Yukio Morita ,  Shigeto Negi ,  Takeo Kanai ,  Eiichi Morita

IPC分类号： C07D501/06 ,  A61K31/545 ,  C07D501/04 ,  C07D501/36

CPC分类号： C07D501/36

摘要： Improved process for the preparation of 7-(2-amino-2-phenyl-acetamido)cephem derivatives of the general formula (I): ##STR1## wherein R.sub.1 is a hydrogwn atom or hydroxyl group, n stands for 0, 1 or 2, and A denotes a nitrogen-containing heterocyclic group or a direct bond coupling directly the sulfur atom and the --(CH.sub.2).sub.n COOH group together, as well as pharmaceutically acceptable salts thereof. The process is not only simple and easy to carry out, but also provides as crystalline precipitate the intended products with a high yield. The 7-(2-amino-2-phenyl-acetamido)cephem derivatives are useful as intermediates for syntheses of antibacterial agents.

摘要翻译： 用于制备通式（I）的7-（2-氨基-2-苯基 - 乙酰氨基）头孢烯衍生物的改进方法：其中R1是氢原子或羟基，n代表0,1或2 ，A表示含氮杂环基团或直接与硫原子和 - （CH 2）n COOH基团偶联的直接键，以及其药学上可接受的盐。 该方法不仅简单易操作，而且可以以高产率提供目标产物的结晶沉淀。 7-（2-氨基-2-苯基 - 乙酰氨基）头孢烯衍生物可用作合成抗菌剂的中间体。