公开(公告)号：US07009890B2

公开(公告)日：2006-03-07

申请号：US10317087

申请日：2002-12-12

申请人： Takanori Yamazoe ,  Hiroshi Yoshigi ,  Takeo Kanai

发明人： Takanori Yamazoe ,  Hiroshi Yoshigi ,  Takeo Kanai

IPC分类号： G11C16/00

CPC分类号： G11C16/26 ,  G11C16/32

摘要： A non-volatile semiconductor memory EEPROM is usually deteriorated depending on the number of times of program and erase operations and application years thereof. A read operation rate of the EEPROM is generally specified to the operation rate considering deterioration of memory and even in the case where the number of times of program and erase operations is rather small and application years are also rather small, the read operation has been conducted at the read operation rate specified considering deterioration of memory. Moreover, when deterioration of memory is advanced exceeding the specified deterioration, the read operation is now disabled in the worst case. In order to overcome such problem, the reference memories are allocated for every erase and program unit block in the EEPROM memory array, the reference memories are also programmed and erased whenever the memories in the block are erased and programmed and the read timing of memory is generated from the read timing of these reference memories. Moreover, the read timing of the reference memories is outputted as an external interface.

公开(公告)号：US06590809B2

公开(公告)日：2003-07-08

申请号：US10040332

申请日：2002-01-09

申请人： Takanori Yamazoe ,  Hiroshi Yoshigi ,  Yoshiaki Kamigaki ,  Kozo Katayama ,  Shinichi Minami ,  Takeo Kanai

发明人： Takanori Yamazoe ,  Hiroshi Yoshigi ,  Yoshiaki Kamigaki ,  Kozo Katayama ,  Shinichi Minami ,  Takeo Kanai

IPC分类号： G11C1604

CPC分类号： G11C16/0433 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/26

摘要： When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.

公开(公告)号：US08050085B2

公开(公告)日：2011-11-01

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C7/10 ,  G11C11/40

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US20090213649A1

公开(公告)日：2009-08-27

申请号：US10521553

申请日：2002-08-29

申请人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

发明人： Masatoshi Takahashi ,  Takanori Yamazoe ,  Kozo Katayama ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Hiroshi Watase ,  Takeo Kanai ,  Nobutaka Nagasaki

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/14 ,  G06F12/14

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975 ,  G07F7/084 ,  G11C11/005 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/16

摘要： A semiconductor processing device according to the invention includes a first non-volatile memory (21) for erasing stored information on a first data length unit, a second non-volatile memory (22) for erasing stored information on a second data length unit, and a central processing unit (2), and capable of inputting/outputting encrypted data from/to an outside. The first non-volatile memory is used for storing an encryption key to be utilized for encrypting the data. The second non-volatile memory is used for storing a program to be processed by the central processing unit. The non-volatile memories to be utilized for storing the program and for storing the encryption key are separated from each other, and the data lengths of the erase units of information to be stored in the non-volatile memories are defined separately. Therefore, the stored information can efficiently be erased before the execution of a processing of writing the program, and the stored information can be erased corresponding to the data length of a necessary processing unit in the write of the encryption key to be utilized in the calculation processing of the CPU.

摘要翻译： 根据本发明的半导体处理装置包括用于擦除第一数据长度单元上存储的信息的第一非易失性存储器（21），用于擦除第二数据长度单元上存储的信息的第二非易失性存储器（22），以及 中央处理单元（2），能够从/向外部输入/输出加密数据。 第一非易失性存储器用于存储要用于加密数据的加密密钥。 第二非易失性存储器用于存储要由中央处理单元处理的程序。 用于存储程序和用于存储加密密钥的非易失性存储器彼此分离，并且存储在非易失性存储器中的信息的擦除单元的数据长度被分开地定义。 因此，在执行写入程序的处理之前可以有效地擦除存储的信息，并且可以根据在计算中要使用的加密密钥的写入中的必要处理单元的数据长度来擦除存储的信息 处理CPU。

公开(公告)号：US07215179B2

公开(公告)日：2007-05-08

申请号：US10535102

申请日：2003-09-26

申请人： Takanori Yamazoe ,  Takeo Kanai

发明人： Takanori Yamazoe ,  Takeo Kanai

IPC分类号： G05F1/10

CPC分类号： G11C5/146 ,  G11C5/145 ,  H02M3/073 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/076

摘要： The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

摘要翻译： 本发明涉及一种非易失性存储器的升压电路，其需要等于或高于电源电压的正或负高电压。 本发明即使在等于或低于3V的低电源电压下也可产生大约12V的高电压，并且不仅通过相同电路产生正高电压而且产生负高电压。 此外，通过将根据本发明的升压电路的身体控制型并联电荷泵与串联型电荷泵组合，可以有效地产生两种类型的高电压，并且可以实现芯片面积的减少 。

公开(公告)号：US20060006925A1

公开(公告)日：2006-01-12

申请号：US10535102

申请日：2003-09-26

申请人： Takanori Yamazoe ,  Takeo Kanai

发明人： Takanori Yamazoe ,  Takeo Kanai

IPC分类号： G05F1/10

CPC分类号： G11C5/146 ,  G11C5/145 ,  H02M3/073 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/076

摘要： The present invention relates to a booster circuit of a non-volatile memory requiring a plus or minus high voltage equal to or higher than a power-supply voltage. The present invention can generate a high voltage of approximately 12 V even at a low power-supply voltage equal to or lower than 3 V and generate not only a plus high voltage but also a minus high voltage by the same circuit. Also, by combining a body-controlled type parallel charge pump, which is a booster circuit according to the present invention, with a serial-type charge pump, two types of high voltages can be efficiently generated and a reduction in chip areas can be achieved.

摘要翻译： 本发明涉及一种非易失性存储器的升压电路，其需要等于或高于电源电压的正或负高电压。 本发明即使在等于或低于3V的低电源电压下也可产生大约12V的高电压，并且不仅通过相同电路产生正高电压而且产生负高电压。 此外，通过将根据本发明的升压电路的身体控制型并联电荷泵与串联型电荷泵组合，可以有效地产生两种类型的高电压，并且可以实现芯片面积的减少 。

公开(公告)号：US20070279191A1

公开(公告)日：2007-12-06

申请号：US11802018

申请日：2007-05-18

申请人： Masaaki Yamamoto ,  Takanori Yamazoe ,  Toshiyuki Kuwana

发明人： Masaaki Yamamoto ,  Takanori Yamazoe ,  Toshiyuki Kuwana

IPC分类号： H04Q5/22

CPC分类号： H04B5/02 ,  G06K7/0008 ,  G06K7/10316 ,  G06K7/10356 ,  G06K7/10435 ,  H04B5/0056 ,  H04B5/0062

摘要： A technique of reducing the interference wave occurred between a plurality of reader/writers in an environment in which a plurality of RFID systems are operating. An RFID system includes a plurality of reader/writers and a controller for controlling the plurality of reader/writers. Each reader/writer includes a body, antennas, and a distributor for selecting one antenna from the antennas. The controller selects an antenna having a positional relationship in which the interference wave is small from the antennas of each reader/writer, and giving a command for the antenna to the body of each reader/writer. Each reader/writer selects one antenna from the antennas based on the command from the controller and transmits a command to the RFID.

摘要翻译： 在多个RFID系统正在工作的环境中，在多个读取器/写入器之间发生减少干扰波的技术。 RFID系统包括多个读取器/写入器和用于控制多个读取器/写入器的控制器。 每个读取器/写入器包括从天线选择一个天线的主体，天线和分配器。 控制器从每个读取器/写入器的天线中选择具有干扰波小的位置关系的天线，并且向每个读取器/写入器的主体给出天线的命令。 每个读取器/写入器根据来自控制器的命令从天线中选择一个天线，并向RFID发送命令。

公开(公告)号：US07254084B2

公开(公告)日：2007-08-07

申请号：US11138344

申请日：2005-05-27

申请人： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

发明人： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC分类号： G11C5/14 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

摘要： A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

公开(公告)号：US20110306378A1

公开(公告)日：2011-12-15

申请号：US13035747

申请日：2011-02-25

申请人： Yuki Himori ,  Shinichiro Fukushima ,  Hiroyuki Hamada ,  Masaaki Yamamoto ,  Takanori Yamazoe

发明人： Yuki Himori ,  Shinichiro Fukushima ,  Hiroyuki Hamada ,  Masaaki Yamamoto ,  Takanori Yamazoe

IPC分类号： H04B7/24

CPC分类号： H04W74/0808 ,  Y02D70/00

摘要： A plurality of masters continuously receives data through a specific channel to detect whether a slave exists nearby. On the other hand, the slave transmits data for a given period through the specific channel by a trigger specified by a user. A master near the slave receives the data transmitted by the slave and recognizes that the slave exists nearby. After the recognition of the slave, the master performs carrier senses on channels other than the specific channel and transmits data for a given period through a channel on which a carrier does not exist. After the transmission through the specific channel, the slave receives a plurality of channels other than the specific channel to receive the data transmitted by the master.

摘要翻译： 多个主机通过特定通道连续地接收数据，以检测从站是否存在于附近。 另一方面，从设备通过特定频道通过用户指定的触发器发送给定周期的数据。 从站附近的主站接收从站发送的数据，并识别从站存在于附近。 在对从机进行识别之后，主设备在特定信道之外的信道上执行载波侦听，并通过不存在载波的信道发送给定周期的数据。 在通过特定信道的传输之后，从机接收除特定信道之外的多个信道，以接收主设备发送的数据。

公开(公告)号：US20080137429A1

公开(公告)日：2008-06-12

申请号：US11971887

申请日：2008-01-09

申请人： Masaaki TERASAWA ,  Yoshiki Kawajiri ,  Takanori Yamazoe

发明人： Masaaki TERASAWA ,  Yoshiki Kawajiri ,  Takanori Yamazoe

IPC分类号： G11C16/06

CPC分类号： G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

摘要： A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

摘要翻译： 从非易失性存储器的低功耗模式的释放到读取操作的重新开始的延迟降低。 可以电重写存储的信息的非易失性存储器在阱区中具有多个非易失性存储单元晶体管，其具有分别耦合到位线和源极线的漏电极和源电极以及耦合到字线的栅电极，并且基于阈值电压之间的差存储信息 读操作中的字线选择电平，而非易失性存储器具有低功耗模式。 在低功耗模式中，将低于电路接地电压并高于读操作所需的第一负电压的第二电压提供给阱区和字线。 当升压形成重写负电压时，负电压的电路节点不是低功耗模式下的电路接地电压。