公开(公告)号：US20060290401A1

公开(公告)日：2006-12-28

申请号：US11455198

申请日：2006-06-19

申请人： Hiroshi Yanagigawa ,  Mitsuru Yoshida

发明人： Hiroshi Yanagigawa ,  Mitsuru Yoshida

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  H02M1/38 ,  H02M2001/385 ,  H03H11/54 ,  H03K5/1515 ,  H03K2005/00143 ,  H03K2005/00202

摘要： In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.

摘要翻译： 在死区时间控制电路中，延迟电路连接到输入端，并且适于延迟通过其相应于死区时间的延迟时间的信号。 逻辑电路具有经由延迟电路连接到输入端子的第一输入端，直接连接到输入端子的第二输入端和连接到输出端子的输出端。 死区时间具有可调节的温度特性。

公开(公告)号：US07400163B2

公开(公告)日：2008-07-15

申请号：US11455198

申请日：2006-06-19

申请人： Hiroshi Yanagigawa ,  Mitsuru Yoshida

发明人： Hiroshi Yanagigawa ,  Mitsuru Yoshida

IPC分类号： H03K17/14 ,  H03K17/284

CPC分类号： H03H11/265 ,  H02M1/38 ,  H02M2001/385 ,  H03H11/54 ,  H03K5/1515 ,  H03K2005/00143 ,  H03K2005/00202

摘要： In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.

摘要翻译： 在死区时间控制电路中，延迟电路连接到输入端，并且适于延迟通过其相应于死区时间的延迟时间的信号。 逻辑电路具有经由延迟电路连接到输入端子的第一输入端，直接连接到输入端子的第二输入端和连接到输出端子的输出端。 死区时间具有可调节的温度特性。

公开(公告)号：US6002158A

公开(公告)日：1999-12-14

申请号：US998923

申请日：1997-12-29

申请人： Hiroshi Yanagigawa

发明人： Hiroshi Yanagigawa

IPC分类号： H01L27/12 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L29/8611

摘要： A high breakdown-voltage diode is provided, which has a decreased chip area and a low electric resistance between anode and cathode regions after the breakdown phenomenon takes place. A semiconductor layer of a first conductivity type is vertically isolated by a first isolation dielectric and laterally isolated by a second isolation dielectric from outside. A first diffusion region of a second conductivity type is formed in a surface area of the semiconductor layer, thereby forming a first p-n junction. A second diffusion region of the first conductivity type is formed in the surface area to be apart from the first diffusion region. A third diffusion region of the second conductivity type is formed in the surface area between the first and second diffusion regions, thereby forming a second p-n junction. The third diffusion region is electrically connected to the first diffusion region. A depletion region formed at the second p-n junction grows according to a reverse voltage applied across the first and second diffusion regions, so that each end of the depletion region extends to a surface of the third diffusion region and to the first isolation dielectric while no breakdown occurs at the first p-n junction, relaxing an electric filed existing near the first p-n junction.

摘要翻译： 提供了高击穿电压二极管，其在击穿现象发生之后具有减小的芯片面积和在阳极和阴极区域之间的低电阻。 第一导电类型的半导体层由第一隔离电介质垂直隔离，并由第二隔离电介质从外部侧向隔离。 第二导电类型的第一扩散区形成在半导体层的表面区域中，从而形成第一p-n结。 第一导电类型的第二扩散区域形成在与第一扩散区域分离的表面区域中。 第二导电类型的第三扩散区形成在第一和第二扩散区之间的表面区域中，从而形成第二p-n结。 第三扩散区域电连接到第一扩散区域。 形成在第二pn结处的耗尽区域根据施加在第一和第二扩散区域上的反向电压而增长，使得耗尽区域的每个端部延伸到第三扩散区域的表面并且在没有击穿的情况下延伸到第一隔离电介质 发生在第一个pn结处，放松在第一个pn结附近存在的电场。

公开(公告)号：US07439795B2

公开(公告)日：2008-10-21

申请号：US11926704

申请日：2007-10-29

申请人： Hiroshi Yanagigawa ,  Masayuki Ida ,  Kazunori Doi

发明人： Hiroshi Yanagigawa ,  Masayuki Ida ,  Kazunori Doi

IPC分类号： G05F3/16 ,  H02M3/04 ,  H02M3/07

CPC分类号： G11C5/145 ,  H02M3/073

摘要： A charge pump circuit is provided with a capacitor for generating a boosted voltage from a power supply voltage in response to a clock signal; and an output node from which the boosted voltage is externally outputted. The capacitor includes a first well formed within a substrate, a second well formed within the first well, first and second diffusion regions formed within the second well to receive the clock signal, a channel region provided between the first and second diffusion regions in which channel region a channel is formed in response to the clock signal; and an electrode positioned over the channel region across a dielectric and connected with the output node. The output node is also connected with the first well to apply said boosted voltage to the first well.

摘要翻译： 电荷泵电路设置有电容器，用于响应于时钟信号从电源电压产生升压电压; 以及从外部输出升压电压的输出节点。 电容器包括形成在衬底内的第一阱，形成在第一阱内的第二阱，形成在第二阱内以接收时钟信号的第一和第二扩散区，设置在第一和第二扩散区之间的沟道区， 区域响应于时钟信号形成通道; 以及电极，其位于所述沟道区域上方跨越电介质并与所述输出节点连接。 输出节点也与第一阱连接，以将所述升压电压施加到第一阱。

公开(公告)号：US07884421B2

公开(公告)日：2011-02-08

申请号：US11882854

申请日：2007-08-06

申请人： Hiroshi Yanagigawa

发明人： Hiroshi Yanagigawa

IPC分类号： H01L29/66

CPC分类号： H01L29/0847 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： In a high voltage MOS transistor, in a portion immediately below the gate electrode, peaks of concentration distribution in depth direction of a first conductivity type impurity and a second conductivity type impurity in the drain offset region are in the same depth, the second conductivity type impurity being higher concentrated than the first conductivity type impurity.

摘要翻译： 在高压MOS晶体管中，在栅电极的正下方的一部分，漏极偏移区域中的第一导电型杂质和第二导电型杂质的深度方向的浓度分布峰值处于相同的深度，第二导电型 杂质比第一导电型杂质浓度高。

公开(公告)号：US07733133B2

公开(公告)日：2010-06-08

申请号：US12314688

申请日：2008-12-15

申请人： Hiroshi Yanagigawa ,  Masaki Kojima

发明人： Hiroshi Yanagigawa ,  Masaki Kojima

IPC分类号： H03K3/00

CPC分类号： H03K17/166 ,  H03K17/0822

摘要： A power switch circuit includes an output transistor which is connected between a first power supply terminal and an output terminal, and drives a load, an abnormality detecting circuit which detects an abnormal state of the output transistor, a resistance element which generates a resistance component by a diffusion layer formed on a well region, and is provided between an input terminal and a control terminal of the output transistor, and a well potential switching circuit which switches a voltage to be supplied to the well region between a voltage of the output terminal and a voltage of a second power supply terminal based on a detection result by the abnormality detecting circuit.

摘要翻译： 电源开关电路包括连接在第一电源端子和输出端子之间并驱动负载的输出晶体管，检测输出晶体管的异常状态的异常检测电路，产生电阻分量的电阻元件 形成在阱区上的扩散层，设置在输出端子与输出晶体管的控制端子之间;阱电位切换电路，在输出端子的电压和 基于异常检测电路的检测结果的第二电源端子的电压。

公开(公告)号：US06384453B1

公开(公告)日：2002-05-07

申请号：US09411364

申请日：1999-10-04

申请人： Hiroshi Yanagigawa

发明人： Hiroshi Yanagigawa

IPC分类号： H01L2362

CPC分类号： H01L29/7824 ,  H01L27/0255 ,  H01L29/402 ,  H01L29/7835 ,  H01L29/8611

摘要： A high withstand voltage diode for protecting a high-voltage transistor has a first region 2 of a second conductivity type formed on the substrate of a first conductivity type, a high-concentration second region 5 of the second type formed on the first region 2, a third region 3 of the first conductivity type formed so as to, be adjacent to the first region 2, a high-concentration fourth region 4 of the first conductivity type formed on the surface of the third region 3, and a gate electrode 7 that straddles the first region 2 and the third region 3 with an intervening gate oxide film, and which is electrically connected to the fourth region.

摘要翻译： 用于保护高压晶体管的高耐压二极管具有形成在第一导电类型的衬底上的第二导电类型的第一区域2，形成在第一区域2上的第二类型的高浓度第二区域5， 第一导电类型的第三区域3形成为与第一区域2相邻，形成在第三区域3的表面上的第一导电类型的高浓度第四区域4和栅极电极7，栅极电极7 用中间的栅极氧化膜跨越第一区域2和第三区域3，并且电连接到第四区域。

公开(公告)号：US20100001314A1

公开(公告)日：2010-01-07

申请号：US12458201

申请日：2009-07-02

申请人： Hiroshi Yanagigawa

发明人： Hiroshi Yanagigawa

IPC分类号： H01L29/747

CPC分类号： H01L29/7813 ,  H01L27/0705 ,  H01L29/0878 ,  H01L29/7397

摘要： A bidirectional switch includes a first switch and a second switch. The switch includes a well region of a first-conductivity-type formed on a semiconductor substrate, and serving as drains of the first switch and the second switch, a gate electrode of the first switch provided in a first trench formed in the well region through a first gate insulating film, a gate electrode of the second switch formed in a second trench formed in the well region so as to be spaced apart from the first trench with a second gate insulating film, a source region of the first switch formed on a side wall of the first trench, and on a surface of the well region via a first channel region of a second-conductivity-type, and a source region of the second switch formed on a side wall of the second trench, and on a surface of the well region via a second channel region of the second-conductivity-type. The well region is formed in a region between the first trench and the second trench.

摘要翻译： 双向开关包括第一开关和第二开关。 开关包括在半导体衬底上形成的第一导电类型的阱区，并且用作第一开关和第二开关的漏极，第一开关的栅电极设置在形成在阱区中的第一沟槽中，通过 第一栅极绝缘膜，第二开关的栅电极，形成在形成在阱区中的第二沟槽中，以与第一沟槽间隔开第二栅极绝缘膜，第一开关的源极区域形成在第一栅极绝缘膜上， 并且经由第二导电类型的第一沟道区和形成在第二沟槽的侧壁上的第二开关的源极区和在表面上的第一沟槽的表面上的表面 通过第二导电型的第二沟道区。 阱区形成在第一沟槽和第二沟槽之间的区域中。

公开(公告)号：US20090179685A1

公开(公告)日：2009-07-16

申请号：US12314688

申请日：2008-12-15

申请人： Hiroshi Yanagigawa ,  Masaki Kojima

发明人： Hiroshi Yanagigawa ,  Masaki Kojima

IPC分类号： H03K17/16

CPC分类号： H03K17/166 ,  H03K17/0822

摘要： A power switch circuit includes an output transistor which is connected between a first power supply terminal and an output terminal, and drives a load, an abnormality detecting circuit which detects an abnormal state of the output transistor, a resistance element which generates a resistance component by a diffusion layer formed on a well region, and is provided between an input terminal and a control terminal of the output transistor, and a well potential switching circuit which switches a voltage to be supplied to the well region between a voltage of the output terminal and a voltage of a second power supply terminal based on a detection result by the abnormality detecting circuit.

摘要翻译： 电源开关电路包括连接在第一电源端子和输出端子之间并驱动负载的输出晶体管，检测输出晶体管的异常状态的异常检测电路，产生电阻分量的电阻元件 形成在阱区上的扩散层，设置在输出端子与输出晶体管的控制端子之间;阱电位切换电路，在输出端子的电压和 基于异常检测电路的检测结果的第二电源端子的电压。

公开(公告)号：US5767556A

公开(公告)日：1998-06-16

申请号：US802949

申请日：1997-02-21

申请人： Hiroshi Yanagigawa

发明人： Hiroshi Yanagigawa

IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7816 ,  H01L29/1079 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/78 ,  H01L29/7801 ,  H01L29/1083

摘要： The invention relates to a field effect transistor that ensures that a threshold voltage does not increase even if a breakdown voltage is increased. The field effect transistor (FET) includes: (a) a first conductivity type semiconductor substrate; (b) a second conductivity type well formed at a surface of the substrate; (c) a first conductivity type well formed at a surface of the second conductivity type well, the first conductivity type well having an impurity concentration profile that varies in a depthwise direction with a maximum impurity concentration located at the deepest vertical position of the first conductivity type well; (d) a second conductivity type source region, formed at a surface of the first conductivity type well; (e) a second conductivity type drain region formed at a surface of the second conductivity type well; (f) a gate insulating film, formed at a surface of the first conductivity type semiconductor substrate between the source and drain regions; (g) a gate electrode, formed on the gate insulating film; (h) a source electrode, formed on the source region; and, (i) a drain electrode, formed on the drain region.

摘要翻译： 本发明涉及一种场效应晶体管，其确保即使击穿电压增加，阈值电压也不会增加。 场效应晶体管（FET）包括：（a）第一导电型半导体衬底; （b）在基板表面形成的第二导电类型; （c）在第二导电类型阱的表面形成的第一导电类型井，具有在深度方向上变化的杂质浓度分布的第一导电类型阱，其中最大杂质浓度位于第一导电类型的最深垂直位置 类型好 （d）形成在所述第一导电类型阱的表面处的第二导电类型源极区; （e）形成在所述第二导电类型阱的表面处的第二导电类型漏极区; （f）在所述源极和漏极区域之间的所述第一导电类型半导体衬底的表面处形成的栅极绝缘膜; （g）形成在栅极绝缘膜上的栅电极; （h）源电极，形成在源极区上; 和（i）形成在漏区上的漏电极。