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    Nonvolatile semiconductor memory device with readout test circuitry
    1.
    发明授权
    Nonvolatile semiconductor memory device with readout test circuitry 失效
    具有读出测试电路的非易失性半导体存储器件

    公开(公告)号：US4819212A

    公开(公告)日：1989-04-04

    申请号：US50717

    申请日：1987-05-18

    申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Isao Sato ,  Shigeru Kumagai ,  Kazuto Suzuki

    发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Isao Sato ,  Shigeru Kumagai ,  Kazuto Suzuki

    IPC分类号： G11C8/12 ,  G11C16/08 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C16/08

    摘要： A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.

    摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，每个存储单元包括非易失性晶体管，多个行线，各行连接到布置在相应行上的存储器单元，多个列线连接到布置的存储单元 在对应的列上，地址缓冲电路，用于在其地址输入端接收外部地址信号，并响应于所接收的外部地址信号输出内部地址信号，连接到列线的列线选择晶体管，列解码电路 用于选择性地偏置列线选择晶体管，用于选择性地偏置行线的行解码电路，以及用于检测由列线选择晶体管选择的列线的电位的数据检测电路。 该装置还包括控制单元，其产生用于控制地址缓冲电路的控制信号，使得内部地址信号被设置为预定值，以将所有行线设置为未选择状态，从而设置列线 通过列线选择晶体管，以预定电位。

    Nonvolatile semiconductor memory device
    2.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US4831592A

    公开(公告)日：1989-05-16

    申请号：US68521

    申请日：1987-07-01

    申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Isao Sato ,  Shigeru Kumagai ,  Kazuto Suzuki

    发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Isao Sato ,  Shigeru Kumagai ,  Kazuto Suzuki

    IPC分类号： G11C16/30 ,  G11C16/32

    CPC分类号： G11C16/32 ,  G11C16/30

    摘要： A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors. It further comprises a second diode connected between the cathode of the first diode and the output node, and a discharging circuit for discharging the cathode of the first diode to a reference voltage level during a time other than a programming mode.

    摘要翻译： 一种非易失性半导体存储器件，包括用于向电容器施加脉冲信号的脉冲信号发生器，连接到电容器的阳极的第一二极管，以编程模式对电容器充电的充电电路，用于防止电位 输出节点从预定电平上升，非易失性MOS晶体管的存储单元，连接到高电压端子的负载MOS晶体管，用于选择排列成一行的一组存储单元的行解码器，连接在 设置在一列中的各组存储单元和负载MOS晶体管，响应于输出节点处的电压以打开或关闭负载MOS晶体管的数据发生器，以及响应于输出节点处的电压以选择性地 激励列栅极MOS晶体管。 其还包括连接在第一二极管的阴极和输出节点之间的第二二极管和用于在编程模式之外的时间期间将第一二极管的阴极放电到参考电压电平的放电电路。

    Semiconductor memory device with address transition actuated dummy cell
    4.
    发明授权
    Semiconductor memory device with address transition actuated dummy cell 失效
    具有地址转换激活的虚拟单元的半导体存储器件

    公开(公告)号：US5191552A

    公开(公告)日：1993-03-02

    申请号：US684567

    申请日：1991-05-31

    申请人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Kazuhisa Kanazawa ,  Shigeru Kumagai ,  Isao Sato

    发明人： Hiroto Nakai ,  Hiroshi Iwahashi ,  Kazuhisa Kanazawa ,  Shigeru Kumagai ,  Isao Sato

    IPC分类号： G11C7/06 ,  G11C16/28

    CPC分类号： G11C7/062 ,  G11C16/28

    摘要： In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

    摘要翻译： 在半导体存储器件中，第一负载电路与列线耦合，第一虚设单元连接到虚拟列线，第二负载电路连接到虚拟列线，第二虚设单元连接到虚拟列 线，并且感测放大器根据列线和虚拟列线之间的电位差来感测存储在存储单元中的数据。 在这样布置的半导体存储器件中，第二虚设单元被正常地设置在导通状态。 第二虚拟单元与虚拟线的连接在行线切换时改变流向虚拟线的电流，从而在行线切换时保持基准电位的上升。