公开(公告)号：US20080258177A1

公开(公告)日：2008-10-23

申请号：US12102777

申请日：2008-04-14

申请人： Hiroyuki IKEDA ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

发明人： Hiroyuki IKEDA ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

IPC分类号： H01L27/088

CPC分类号： H01L27/11 ,  G11C5/14 ,  H01L27/0207

摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

摘要翻译： 连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。 因此，从开关电路单元的开关动作无效。 连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。 因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。

公开(公告)号：US07073147B2

公开(公告)日：2006-07-04

申请号：US10694825

申请日：2003-10-29

申请人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

发明人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

IPC分类号： G06F17/50

CPC分类号： H01L27/11 ,  G11C5/14 ,  H01L27/0207

摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

摘要翻译： 连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。 因此，从开关电路单元的开关动作无效。 连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。 因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。

公开(公告)号：US20060214721A1

公开(公告)日：2006-09-28

申请号：US11435093

申请日：2006-05-17

申请人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

发明人： Hiroyuki Ikeda ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

IPC分类号： H03K17/00

CPC分类号： H01L27/11 ,  G11C5/14 ,  H01L27/0207

摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

摘要翻译： 连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。 因此，从开关电路单元的开关动作无效。 连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。 因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。

公开(公告)号：US20120268167A1

公开(公告)日：2012-10-25

申请号：US13540198

申请日：2012-07-02

申请人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

发明人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

IPC分类号： H03K19/094

CPC分类号： H03K3/356165 ,  H03K3/012 ,  H03K3/356182 ,  H03K19/018507

摘要： A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

摘要翻译： 如果在上拉电路（总线保持电路）的电源电压和输入端子之间发生电位差，则上拉电路防止产生泄漏电流。 总线保持电路中设置有控制端子。 输入端子和控制端子的输入被输入到或非门，并且NOR门的输出被输入到控制输入端子和总线保持电源电压之间的耦合的第一MOSFET的栅极端子 电路。 提供第二个MOSFET（控制MOSFET）作为由控制端子的反相输出操作的开关。 通过串联耦合第一个MOSFET和控制MOSFET，可以以更高的精度控制输入端子和电源电压之间的耦合，从而防止漏电流的产生。

公开(公告)号：US20110062990A1

公开(公告)日：2011-03-17

申请号：US12871529

申请日：2010-08-30

申请人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

发明人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K3/356165 ,  H03K3/012 ,  H03K3/356182 ,  H03K19/018507

摘要： A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

摘要翻译： 如果在上拉电路（总线保持电路）的电源电压和输入端子之间发生电位差，则上拉电路防止产生泄漏电流。 总线保持电路中设置有控制端子。 输入端子和控制端子的输入被输入到或非门，并且NOR门的输出被输入到控制输入端子和总线保持电源电压之间的耦合的第一MOSFET的栅极端子 电路。 提供第二个MOSFET（“控制”MOSFET）作为通过控制端子的反相输出操作的开关。 通过串联耦合第一个MOSFET和控制MOSFET，可以以更高的精度控制输入端子和电源电压之间的耦合，从而防止漏电流的产生。

公开(公告)号：US08237469B2

公开(公告)日：2012-08-07

申请号：US12871529

申请日：2010-08-30

申请人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

发明人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

IPC分类号： H03K19/094

CPC分类号： H03K3/356165 ,  H03K3/012 ,  H03K3/356182 ,  H03K19/018507

摘要： A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

摘要翻译： 如果在上拉电路（总线保持电路）的电源电压和输入端子之间发生电位差，则上拉电路防止产生泄漏电流。 总线保持电路中设置有控制端子。 输入端子和控制端子的输入被输入到或非门，并且NOR门的输出被输入到控制输入端子和总线保持电源电压之间的耦合的第一MOSFET的栅极端子 电路。 提供第二个MOSFET（“控制”MOSFET）作为通过控制端子的反相输出操作的开关。 通过串联耦合第一个MOSFET和控制MOSFET，可以以更高的精度控制输入端子和电源电压之间的耦合，从而防止漏电流的产生。

公开(公告)号：US06967881B2

公开(公告)日：2005-11-22

申请号：US10785101

申请日：2004-02-25

申请人： Toshio Sasaki ,  Toshio Yamada

发明人： Toshio Sasaki ,  Toshio Yamada

IPC分类号： H01L21/822 ,  G11C16/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03K19/00 ,  G11C11/00

CPC分类号： G11C29/802 ,  G11C16/0441 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/1208 ,  G11C2029/4402 ,  H01L27/115 ,  H01L2223/5444

摘要： A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.

摘要翻译： 半导体集成电路使用连接到专用信号线的熔丝电路的非易失性存储单元，而不使用连接到公共总线的旨在用于通用的非易失性存储器，以便存储用于缺陷消除的控制信息，并且 像电路模块一样。 控制信息的存储的可靠性不限于旨在用于通用目的的非易失性存储器中的信息的存储性能，并且可以容易地增强控制信息的存储的可靠性。 由于用于传送控制信息的第二布线是专用于其传送的布线，所以不需要在用于电路模块中的实际操作的电路部分的连接和它们的控制之间进行切换。 可以简化用于传送控制信息的电路配置。

公开(公告)号：US06762969B2

公开(公告)日：2004-07-13

申请号：US10346097

申请日：2003-01-17

申请人： Toshio Sasaki ,  Toshio Yamada

发明人： Toshio Sasaki ,  Toshio Yamada

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C16/0441 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/1208 ,  G11C2029/4402 ,  H01L27/115 ,  H01L2223/5444

摘要： A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.

摘要翻译： 半导体集成电路使用连接到专用信号线的熔丝电路的非易失性存储单元，而不使用连接到公共总线的旨在用于通用的非易失性存储器，以便存储用于缺陷消除的控制信息，并且 像电路模块一样。 控制信息的存储的可靠性不限于旨在用于通用目的的非易失性存储器中的信息的存储性能，并且可以容易地增强控制信息的存储的可靠性。 由于用于传送控制信息的第二布线是专用于其传送的布线，所以不需要在用于电路模块中的实际操作的电路部分的连接和它们的控制之间进行切换。 可以简化用于传送控制信息的电路配置。

公开(公告)号：US07858168B2

公开(公告)日：2010-12-28

申请号：US12410796

申请日：2009-03-25

申请人： Toshio Yamada ,  Takeshi Tokunaga ,  Makoto Furutani

发明人： Toshio Yamada ,  Takeshi Tokunaga ,  Makoto Furutani

IPC分类号： B32B3/12

CPC分类号： B01D46/247 ,  B01D46/2418 ,  B01D46/2451 ,  B01D46/2459 ,  B01D46/2466 ,  B01D46/2474 ,  B01D2046/2481 ,  B01D2046/2485 ,  B01D2046/2488 ,  B01D2046/2496 ,  B01D2279/30 ,  B28B11/006 ,  B28B11/007 ,  F01N3/2828 ,  F01N2330/06 ,  F01N2330/32 ,  F01N2330/48 ,  Y10T428/24149 ,  Y10T428/24157 ,  Y10T428/24165

摘要： There is disclosed a honeycomb structure in which while sufficiently maintaining a collection efficiency and a bonding strength of a plugging portion, a thermal shock resistance is improved. A plugging portion 32 is formed in the end of each cell 3 of a honeycomb structure 1, and a gap 34 having a size of 20 μm or more is formed between the plugging portion 32 and each partition wall 2. Moreover, the length of the gap 34 in the axial direction is 50% or more and less than 95% of the length of the plugging portion 32 in the axial direction, the length of the gap in a face vertical to the axial direction is 20% or more and 50% or less of the length of the inner peripheral surface of the cell 3, and the gaps are formed in at least ⅓ of the plugging portions 32.

摘要翻译： 公开了一种蜂窝结构体，其中，尽管充分保持了封堵部分的收集效率和接合强度，但是耐热冲击性得到改善。 在蜂窝结构体1的每个电池单元3的端部形成有堵塞部分32，并且在封堵部分32和每个分隔壁2之间形成尺寸为20μm或更大的间隙34。 轴向的间隙34为堵塞部32的轴向长度的50％以上且小于95％，与轴方向垂直的面的间隙的长度为20％以上且50％以上， 或更小的单元3的内周表面的长度，并且在至少1/3的封堵部分32中形成间隙。

公开(公告)号：US07645427B2

公开(公告)日：2010-01-12

申请号：US10667339

申请日：2003-09-23

申请人： Shogo Hirose ,  Toshio Yamada

发明人： Shogo Hirose ,  Toshio Yamada

IPC分类号： F01N3/022 ,  F01N3/023 ,  F01N3/24

CPC分类号： B01D46/247 ,  B01D46/0063 ,  B01D46/2451 ,  B01D46/2455 ,  B01D46/2466 ,  B01D46/2474 ,  B01D2046/2477 ,  B01D2046/2481 ,  B01D2046/2488 ,  B01D2046/2496 ,  B01J35/04 ,  F01N3/0222 ,  F01N2260/16 ,  F01N2330/06 ,  F01N2330/30 ,  Y02T10/20 ,  Y10S55/30 ,  Y10T29/49345

摘要： There is provided a honeycomb structure usable in a filter for trapping/collecting particulates included in exhaust gas and in which ashes deposited inside can be removed without requiring any special mechanism or apparatus or without detaching the filter from an exhaust system. The honeycomb structure includes: a plurality of through channels 9 separated by porous partition walls 7 and extending in the axial direction of the honeycomb structure; and plugging portions 11 for plugging one end of each of predetermined through channels 9a and an opposite end of each of the rest of through channels 9b in a checkered flag pattern, alternately. In the honeycomb structure, at least one slit 15 per through channel is formed in the vicinity of the plugging portions 11 of the partition walls 7 surrounding the respective through channels 9b.

摘要翻译： 提供了一种可用于捕集/收集废气中所含的微粒的过滤器的蜂窝结构，其中可以除去内部沉积的灰烬，而不需要任何特殊的机构或装置，或者不将过滤器从排气系统分离。 蜂窝结构体包括：多孔分隔壁7分隔开并沿蜂窝结构体的轴向延伸的多个通道9; 以及堵塞部分11，用于以预定的通道9a和其余贯通通道9b的每一个的相对端交替地插入方格标志图案。 在蜂窝结构体中，在贯通通道9b的分隔壁7的封堵部11附近，形成有贯通通道的至少一个狭缝15。