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    Honeycomb structure, manufacturing method of the structure, and exhaust gas purification system using the structure
    1.
    发明授权
    Honeycomb structure, manufacturing method of the structure, and exhaust gas purification system using the structure 有权
    蜂窝结构，结构的制造方法和使用该结构的废气净化系统

    公开(公告)号：US07645427B2

    公开(公告)日：2010-01-12

    申请号：US10667339

    申请日：2003-09-23

    申请人： Shogo Hirose ,  Toshio Yamada

    发明人： Shogo Hirose ,  Toshio Yamada

    IPC分类号： F01N3/022 ,  F01N3/023 ,  F01N3/24

    CPC分类号： B01D46/247 ,  B01D46/0063 ,  B01D46/2451 ,  B01D46/2455 ,  B01D46/2466 ,  B01D46/2474 ,  B01D2046/2477 ,  B01D2046/2481 ,  B01D2046/2488 ,  B01D2046/2496 ,  B01J35/04 ,  F01N3/0222 ,  F01N2260/16 ,  F01N2330/06 ,  F01N2330/30 ,  Y02T10/20 ,  Y10S55/30 ,  Y10T29/49345

    摘要： There is provided a honeycomb structure usable in a filter for trapping/collecting particulates included in exhaust gas and in which ashes deposited inside can be removed without requiring any special mechanism or apparatus or without detaching the filter from an exhaust system. The honeycomb structure includes: a plurality of through channels 9 separated by porous partition walls 7 and extending in the axial direction of the honeycomb structure; and plugging portions 11 for plugging one end of each of predetermined through channels 9a and an opposite end of each of the rest of through channels 9b in a checkered flag pattern, alternately. In the honeycomb structure, at least one slit 15 per through channel is formed in the vicinity of the plugging portions 11 of the partition walls 7 surrounding the respective through channels 9b.

    摘要翻译： 提供了一种可用于捕集/收集废气中所含的微粒的过滤器的蜂窝结构，其中可以除去内部沉积的灰烬，而不需要任何特殊的机构或装置，或者不将过滤器从排气系统分离。 蜂窝结构体包括：多孔分隔壁7分隔开并沿蜂窝结构体的轴向延伸的多个通道9; 以及堵塞部分11，用于以预定的通道9a和其余贯通通道9b的每一个的相对端交替地插入方格标志图案。 在蜂窝结构体中，在贯通通道9b的分隔壁7的封堵部11附近，形成有贯通通道的至少一个狭缝15。

    Semiconductor Device and Method of Controlling the Same
    2.
    发明申请
    Semiconductor Device and Method of Controlling the Same 审中-公开
    半导体器件及其控制方法

    公开(公告)号：US20120268167A1

    公开(公告)日：2012-10-25

    申请号：US13540198

    申请日：2012-07-02

    申请人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

    发明人： Toshio Yamada ,  Kazuo Tanaka ,  Akinobu Watanabe ,  Shigeru Yamamoto ,  Yukio Hiraiwa

    IPC分类号： H03K19/094

    CPC分类号： H03K3/356165 ,  H03K3/012 ,  H03K3/356182 ,  H03K19/018507

    摘要： A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

    摘要翻译： 如果在上拉电路（总线保持电路）的电源电压和输入端子之间发生电位差，则上拉电路防止产生泄漏电流。 总线保持电路中设置有控制端子。 输入端子和控制端子的输入被输入到或非门，并且NOR门的输出被输入到控制输入端子和总线保持电源电压之间的耦合的第一MOSFET的栅极端子 电路。 提供第二个MOSFET（控制MOSFET）作为由控制端子的反相输出操作的开关。 通过串联耦合第一个MOSFET和控制MOSFET，可以以更高的精度控制输入端子和电源电压之间的耦合，从而防止漏电流的产生。

    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07486544B2

    公开(公告)日：2009-02-03

    申请号：US11826636

    申请日：2007-07-17

    申请人： Ryo Mori ,  Toshio Yamada ,  Tetsuya Muraya

    发明人： Ryo Mori ,  Toshio Yamada ,  Tetsuya Muraya

    IPC分类号： G11C11/00 ,  G11C5/14

    CPC分类号： G11C11/412

    摘要： The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.

    摘要翻译： 本发明提供一种半导体集成电路器件，其具有泄漏电流降低的SRAM。 在包括多个存储单元的SRAM中，每个存储单元由两个反相器电路的输入和输出端子交叉存储的存储器构成，以及设置在存储和互补位线之间并且其栅极连接到字线的选择MOSFET， 提供了衬底偏置开关电路。 在正常操作中，衬底偏置开关电路将电源电压提供给形成存储单元的P沟道MOSFET的N型阱，并将电路的接地电位提供给P型阱，其中， 形成N沟道MOSFET。 在待机状态下，衬底偏置开关电路提供低于电源电压的预定电压，并且N型阱和P沟道MOSFET的源极之间的PN结未被正向偏置到N 并且提供比地电位高的预定电压，并且P型阱和N沟道MOSFET的源极之间的PN结未被正向偏置到P型阱。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 审中-公开
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20080258177A1

    公开(公告)日：2008-10-23

    申请号：US12102777

    申请日：2008-04-14

    申请人： Hiroyuki IKEDA ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

    发明人： Hiroyuki IKEDA ,  Toshio Sasaki ,  Akinobu Watanabe ,  Toshio Yamada ,  Akihisa Uchida

    IPC分类号： H01L27/088

    CPC分类号： H01L27/11 ,  G11C5/14 ,  H01L27/0207

    摘要： Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

    摘要翻译： 连接到用于衬底偏置电路的从属开关电路单元的栅电极的布线分别电连接到用于电源电位的布线和用于参考电位的布线。 因此，从开关电路单元的开关动作无效。 连接到各个电路单元的n个阱的布线电连接到用于电源电位的布线，并且连接到各个电路单元的p阱的布线电连接到布线。 因此，n个阱被固定到电源电位，并且p阱被固定到参考电位。

    Semiconductor integrated circuit and IC card
    6.
    发明授权
    Semiconductor integrated circuit and IC card 失效
    半导体集成电路和IC卡

    公开(公告)号：US07317658B2

    公开(公告)日：2008-01-08

    申请号：US11377351

    申请日：2006-03-17

    申请人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

    发明人： Yoshio Takazawa ,  Toshio Yamada ,  Shinichi Ozawa ,  Takeo Kanai ,  Minoru Katoh ,  Koudou Yamauchi ,  Toshihiro Araki

    IPC分类号： G11C8/00

    CPC分类号： G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G11C17/12 ,  G11C2207/2227

    摘要： A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

    摘要翻译： 半导体集成电路具有可以进入活动状态或待机状态的存储器，并且存储器具有用于存储单元连接的位线和源极线的电压产生电路。 响应于从活动状态转换到待机状态的指令，电压产生电路使位线的电位和源极线的电位彼此相等。 响应于从待机状态转换到活动状态的指令，电压产生电路产生位线和源极线之间的电位差。 在待机状态下，位线的电位和源极线的电位彼此相等。 因此，每个存储单元的源极和漏极之间不会发生次阈值泄漏。 在活动状态下，源极线电位不变。

    Honeycomb catalytic body and process for manufacturing honeycomb catalytic body
    7.
    发明申请
    Honeycomb catalytic body and process for manufacturing honeycomb catalytic body 有权
    蜂窝催化体及蜂窝催化体制造工艺

    公开(公告)号：US20070049492A1

    公开(公告)日：2007-03-01

    申请号：US11511461

    申请日：2006-08-29

    申请人： Yukio Miyairi ,  Toshio Yamada

    发明人： Yukio Miyairi ,  Toshio Yamada

    IPC分类号： B01J23/00

    CPC分类号： B01J35/04 ,  B01J23/40 ,  B01J23/63 ,  B01J35/002 ,  B01J35/10 ,  B01J37/0215 ,  B01J37/343

    摘要： A honeycomb catalyst body includes: porous partition walls having a large number of pores and disposed to form a plurality of cells communicating between two end faces, plugged portions disposed to plug each of the cells on one of the end faces, and catalyst layers loaded in layers on an inner surface of the cells and an inner surface of the pores and containing a noble metal. Mass (Mc) of the noble metal contained in the catalyst layer loaded on the inner surface of the cells and mass (Mp) of the noble metal contained in the catalyst layer loaded on the inner surface of the pores satisfy the relation of (Mp)/(Mc)≧4. The honeycomb catalyst body is excellent in purification efficiency, has low pressure loss, and is mountable even in a limited space.

    摘要翻译： 一种蜂窝状催化剂体，具有：具有多个孔的多孔分隔壁，并且设置成形成在两个端面之间连通的多个单元，设置成堵塞其中一个端面上的每个单元的堵塞部分，以及装载在 在细胞的内表面上的层和孔的内表面并含有贵金属。 包含在负载在电池内表面上的催化剂层中的贵金属的质量（M SUB）和催化剂中所含的贵金属的质量（M> P） 填充在孔的内表面上的层满足（M p>）））/>>）= 4的关系。 蜂窝状催化剂体的净化效率优异，压力损失小，即使在有限的空间也能够安装。