公开(公告)号：US4868420A

公开(公告)日：1989-09-19

申请号：US273729

申请日：1988-11-18

申请人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

发明人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

IPC分类号： H03K3/037 ,  H03K3/2885

CPC分类号： H03K3/2885 ,  H03K3/0375

摘要： An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.

摘要翻译： 提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。 触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。 逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。 逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。 根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。

公开(公告)号：US4942320A

公开(公告)日：1990-07-17

申请号：US208118

申请日：1988-06-17

申请人： Hiroyuki Itoh ,  Toshio Yamada ,  Akira Masaki ,  Tohru Kobayashi

发明人： Hiroyuki Itoh ,  Toshio Yamada ,  Akira Masaki ,  Tohru Kobayashi

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K17/16 ,  H03K19/0033 ,  H03K19/086

摘要： A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit. It is disposed in a feedback part and used as a constant current source in a logic circuit comprising a logic part consisting of a differential transistor circuit and the feedback part for negatively feeding back the in-phase output of the differential transistor circuit.

摘要翻译： 本发明的晶体管电路包括用于在其基极处接收第一偏压的第一晶体管，连接到第一晶体管的集电极的电阻器件和连接到第一晶体管和电阻器装置之间的结的钳位装置， 电阻器的端子与其与第一晶体管的连接相对。 当在第一晶体管中产生由于α射线引起的噪声电流并且输出降低时，钳位装置以使得电流流过钳位装置并防止输出变化的方式工作。 本发明的晶体管电路连接到电阻器或晶体管，并作为恒流电路用于向电阻器或晶体管提供电流，使得流过其中的电流恒定。 例如，它被用作射极跟随器的恒流源来构成电平移位电路。 它被布置在反馈部分中，并在逻辑电路中用作恒流源，该逻辑电路包括由差分晶体管电路和反馈部分组成的逻辑部分，用于对差分晶体管电路的同相输出进行负反馈。

公开(公告)号：US5018000A

公开(公告)日：1991-05-21

申请号：US367046

申请日：1989-06-16

申请人： Toshio Yamada ,  Tohru Kobayashi ,  Hirotaka Nishizawa ,  Hiroyuki Itoh ,  Tatsuya Saitoh

发明人： Toshio Yamada ,  Tohru Kobayashi ,  Hirotaka Nishizawa ,  Hiroyuki Itoh ,  Tatsuya Saitoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H03K17/60 ,  H03K19/003

CPC分类号： H01L27/0647

摘要： A MIS capacitor to be implemented in a semiconductor device employing various or predetermined circuits, has a dielectric side electrode which is in contact with a buried layer provided on a semiconductor substrate through a dielectric film and a buried layer-side electrode connected to the buried layer. The buried layer-side electrode of the MIS capacitor is connected to a low-impedance side of the circuit employed therewith. This structure, when connected as such, is capable of reducing the influence of noise attributed to an .alpha.-ray and thereby operating the circuit stably. The semiconductor device using a MIS capacitor invention is adaptable to an emitter follower circuit and various logic circuits for preventing malfunction resulting from .alpha.-ray radiation.

摘要翻译： 在采用各种或预定电路的半导体器件中实现的MIS电容器具有通过电介质膜与设置在半导体衬底上的掩埋层接触的电介质侧电极和连接到掩埋层的掩埋层侧电极 。 MIS电容器的掩埋层侧电极与使用的电路的低阻抗侧连接。 当这样连接时，该结构能够减少归因于α射线的噪声的影响，从而稳定地操作电路。 使用MIS电容器发明的半导体器件适用于射极跟随器电路和用于防止由α射线辐射引起的故障的各种逻辑电路。

公开(公告)号：US5396198A

公开(公告)日：1995-03-07

申请号：US118178

申请日：1993-09-09

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Keiichirou Nakanishi ,  Tatsuya Saitoh ,  Tohru Kobayashi ,  Satoru Isomura

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Keiichirou Nakanishi ,  Tatsuya Saitoh ,  Tohru Kobayashi ,  Satoru Isomura

IPC分类号： H01L23/528 ,  H01L23/66 ,  H01P5/12 ,  H01P1/26

CPC分类号： H01L23/5286 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011

摘要： A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.

摘要翻译： 电源线为构成电子电路装置的各电子线路供电。 负载电路在电子线路中发生的电压噪声的到达时间的范围内连接到电源布线，时间为电子操作时的噪声电流的脉冲宽度的大约一半 电路。 这些负载电路中的每一个都包括电阻和电容的串联电路。

公开(公告)号：US4940905A

公开(公告)日：1990-07-10

申请号：US426047

申请日：1989-10-24

申请人： Tohru Kobayashi ,  Masato Hamamoto ,  Toshio Yamada

发明人： Tohru Kobayashi ,  Masato Hamamoto ,  Toshio Yamada

IPC分类号： H03K3/037 ,  H03K3/2885

CPC分类号： H03K3/2885 ,  H03K3/0375

摘要： An ECL flip-flop circuit has a data holding differential transistor pair and a feedback circuit provided between the collectors and bases of this differential transistor pair. The feedback circuit includes a resistor connected between the bases of the data holding differential transistor pair, a pair of switching means for selectively terminating one end or the other of the resistor, and a pair of feedback transistors each adapted to receive at its base the collector potential of one transistor or the other of the differential transistor pair and to form an emitter follower circuit with the resistor selectively included therein. Thus, it is possible to prevent a malfunction of the ECl flip-flop circuit due to .alpha.-particles or the like.

摘要翻译： ECL触发器电路具有数据保持差分晶体管对和设置在该差分晶体管对的集电极和基极之间的反馈电路。 反馈电路包括连接在数据保持差分晶体管对的基极之间的电阻器，用于选择性地端接电阻器的一端或另一端的一对开关装置，以及一对反馈晶体管，每个反馈晶体管适于在其基极处接收集电极 一个晶体管或另一个差分晶体管对的电位并且形成具有选择性地包括在其中的电阻的射极跟随器电路。 因此，可以防止由于α-粒子等导致的ECl触发器电路的故障。

公开(公告)号：US4891531A

公开(公告)日：1990-01-02

申请号：US256863

申请日：1988-10-12

申请人： Tohru Kobayashi ,  Masato Hamamoto ,  Toshio Yamada

发明人： Tohru Kobayashi ,  Masato Hamamoto ,  Toshio Yamada

IPC分类号： H03K3/286 ,  H03K3/037 ,  H03K3/2885 ,  H03K19/003

CPC分类号： H03K3/2885 ,  H03K3/0375

摘要： An ECL flip-flop circuit has a data holding differential transistor pair and a feedback circuit provided between the collectors and bases of this differential transistor pair. The feedback circuit includes a resistor connected between the bases of the data holding differential transistor pair, a pair of switching means for selectively terminating one end or the other of the resistor, and a pair of feedback transistors each adapted to receive at its base the collector potential of one transistor or the other of the differential transistor pair and to form an emitter follower circuit with the resistor selectively included therein. Thus, it is possible to prevent a malfunction of the ECL flip-flop circuit due to .alpha.-particles or the like.

摘要翻译： ECL触发器电路具有数据保持差分晶体管对和设置在该差分晶体管对的集电极和基极之间的反馈电路。 反馈电路包括连接在数据保持差分晶体管对的基极之间的电阻器，用于选择性地端接电阻器的一端或另一端的一对开关装置，以及一对反馈晶体管，每个反馈晶体管适于在其基极处接收集电极 一个晶体管或另一个差分晶体管对的电位并且形成具有选择性地包括在其中的电阻的射极跟随器电路。 因此，可以防止由于α-粒子等引起的ECL触发器电路的故障。

公开(公告)号：US5298802A

公开(公告)日：1994-03-29

申请号：US56798

申请日：1993-05-03

申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

摘要翻译： 根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。 射极跟随器输出电路由相位分离电路的反相输出驱动。 同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动 电路。 作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。 输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。 由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。 在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。 此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

公开(公告)号：US5283480A

公开(公告)日：1994-02-01

申请号：US557109

申请日：1990-07-25

申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

公开(公告)号：US5059819A

公开(公告)日：1991-10-22

申请号：US133915

申请日：1987-12-16

申请人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

发明人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

IPC分类号： G01R31/3185 ,  H01L27/02

CPC分类号： H01L27/0207 ,  G01R31/318538 ,  G01R31/318572

摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

摘要翻译： 触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据 。 结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。

公开(公告)号：US5055710A

公开(公告)日：1991-10-08

申请号：US520875

申请日：1990-05-09

申请人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

发明人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

IPC分类号： G01R31/3185 ,  H01L27/02

CPC分类号： H01L27/0207 ,  G01R31/318538 ,  G01R31/318572

摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

摘要翻译： 触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据 。 结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。