公开(公告)号：US4868420A

公开(公告)日：1989-09-19

申请号：US273729

申请日：1988-11-18

申请人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

发明人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

IPC分类号： H03K3/037 ,  H03K3/2885

CPC分类号： H03K3/2885 ,  H03K3/0375

摘要： An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.

摘要翻译： 提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。 触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。 逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。 逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。 根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。

公开(公告)号：US4999520A

公开(公告)日：1991-03-12

申请号：US330461

申请日：1989-03-30

申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K3/2885 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K19/086

摘要： A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

摘要翻译： 一种半导体集成电路，其中输入电路由相位分离电路形成，该相位分离电路由输出来自集电极的反相输出和从发射极输出的非反相输出的双极晶体管构成，射极跟随器输出电路由反相输出驱动 同相分流电路，射极跟随器输出电路的发射极负载由晶体管形成，发射极负载晶体管通过非反相输出的上升沿的待充电电容的充电电流暂时驱动导通 的相分离电路。

公开(公告)号：US5298802A

公开(公告)日：1994-03-29

申请号：US56798

申请日：1993-05-03

申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

摘要翻译： 根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。 射极跟随器输出电路由相位分离电路的反相输出驱动。 同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动 电路。 作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。 输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。 由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。 在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。 此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

公开(公告)号：US5283480A

公开(公告)日：1994-02-01

申请号：US557109

申请日：1990-07-25

申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

公开(公告)号：US5870289A

公开(公告)日：1999-02-09

申请号：US572747

申请日：1995-12-14

申请人： Masahide Tokuda ,  Takeshi Kato ,  Hiroyuki Itoh ,  Masayoshi Yagyu ,  Yuuji Fujita ,  Mitsuo Usami

发明人： Masahide Tokuda ,  Takeshi Kato ,  Hiroyuki Itoh ,  Masayoshi Yagyu ,  Yuuji Fujita ,  Mitsuo Usami

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L21/98 ,  H01L23/12 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/40 ,  H05K1/14 ,  H05K1/16 ,  H05K7/02 ,  H05K7/06

CPC分类号： H01L21/6836 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/83192 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/303 ,  H05K3/4007

摘要： A structure for connecting an integrated circuit chip to a wiring substrate which implements high-density packaging, high-density connection, high-speed signal transmission, and low cost. An integrated circuit is connected to a wiring substrate by means of flip-chip die bonding using an adhesive film. A direct through-hole connection is formed directly below a connecting pad so as to pass through the adhesive film and the wiring substrate. This direct through-hole connection directly connects the connecting pad to the wire. As a result of reduced area and thickness of the chip, the chip is mounted in high density, and high-density inputs and outputs are implemented by means of minute two-dimensional connections. Short wire connections directly connected to the chip permit high speed signal transmission, and high reliability is ensured by the dispersion of stress. Low-cost packaging can be effected by simple processes and facilities.

摘要翻译： 用于将集成电路芯片连接到实现高密度封装，高密度连接，高速信号传输和低成本的布线基板的结构。 集成电路通过使用粘合膜的倒装芯片贴片连接到布线基板。 直接通孔连接形成在连接焊盘的正下方，以穿过粘合膜和布线基板。 这种直接通孔连接将连接垫直接连接到电线。 由于芯片的面积和厚度减小，芯片以高密度安装，高密度输入和输出通过微小的二维连接来实现。 直接连接到芯片的短线连接允许高速信号传输，并且通过应力分散来确保高可靠性。 低成本的包装可以通过简单的工艺和设施来实现。

公开(公告)号：US5214318A

公开(公告)日：1993-05-25

申请号：US638568

申请日：1991-01-07

申请人： Keiichirou Nakanishi ,  Mararu Osanai ,  Minoru Yamada ,  Masakazu Yamamoto ,  Akira Masaki ,  Mitsuo Usami

发明人： Keiichirou Nakanishi ,  Mararu Osanai ,  Minoru Yamada ,  Masakazu Yamamoto ,  Akira Masaki ,  Mitsuo Usami

IPC分类号： H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H03F3/45 ,  H03K5/151 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  H04B3/00

CPC分类号： H03K5/151 ,  H03K19/0136 ,  H03K19/01831 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device has, in one embodiment, a pair of signal transmission lines formed over and insulated from a semiconductor substrate, a first circuit formed in the semiconductor substrate and electrically connected with one end of the pair of signal transmission lines for sending an electric signal, and a second circuit formed in the semiconductor substrate and electrically connected with the other end of the pair of signal transmission lines for receiving the electric signal propagating over the transmission line pair. A control resistance is electrically connected between the pair of transmission lines at the above-mentioned other end for controlling a delay time of the signal propagating over the pair of signal transmission lines between the opposite ends of the pair of signal transmission lines.

摘要翻译： 在一个实施例中，半导体集成电路器件具有形成在半导体衬底上并与其绝缘的一对信号传输线，形成在半导体衬底中并与该对信号传输线的一端电连接的第一电路，用于发送 电信号和形成在半导体衬底中并与该对信号传输线的另一端电连接的第二电路，用于接收在传输线对上传播的电信号。 控制电阻电连接在上述另一端的一对传输线之间，用于控制在一对信号传输线的相对端之间在一对信号传输线上传播的信号的延迟时间。

公开(公告)号：US08017441B2

公开(公告)日：2011-09-13

申请号：US12303066

申请日：2006-06-02

申请人： Mitsuo Usami

发明人： Mitsuo Usami

IPC分类号： H01L21/00

CPC分类号： H01L21/56 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： An IC tag inlet (100) is configured by: an upper side antenna (102) and a lower side antenna (103) sandwiching a semiconductor chip (101) that includes an upper electrode (132) and a lower electrode (133) from both upper and lower directions; and a support resin (104) covering the semiconductor chip (101). The semiconductor chip (101) is a micro chip having an outer size of 0.15 mm square or smaller, and a thickness of 10 μm or smaller. In a manufacturing process of the IC tag inlet (100), in order to make the handling of the semiconductor chip (101) easy, prior to a step of sandwiching the semiconductor chip (101) between the upper side antenna (102) and the lower side antenna (103), the whole surface of the semiconductor chip (101) is covered by the support resin (104), so that an effective volume is made large.

摘要翻译： IC标签入口（100）通过以下方式构成：上下侧天线（102）和下侧天线（103），其夹着半导体芯片（101），其包括来自两者的上电极（132）和下电极（133） 上下方向; 和覆盖半导体芯片（101）的支撑树脂（104）。 半导体芯片（101）是外形尺寸为0.15mm以下，厚度为10μm以下的微型芯片。 在IC标签入口（100）的制造过程中，为了使半导体芯片（101）的处理容易，在将半导体芯片（101）夹在上侧天线（102）和 下侧天线（103），半导体芯片（101）的整个表面被支撑树脂（104）覆盖，使得有效体积变大。

公开(公告)号：US07652360B2

公开(公告)日：2010-01-26

申请号：US11696028

申请日：2007-04-03

申请人： Mitsuo Usami

发明人： Mitsuo Usami

IPC分类号： H01L23/02

CPC分类号： H01L24/01 ,  G06K7/0008 ,  G06K19/02 ,  G06K19/041 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07758 ,  G06K19/07786 ,  H01L21/50 ,  H01L23/051 ,  H01L23/08 ,  H01L23/291 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/4827 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/83 ,  H01L2223/6677 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/83801 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/16588 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/83205

摘要： An electronic device, in which a flat plate semiconductor and dumets connected to surface electrodes on the front and back surfaces of the semiconductor and to lead wires are encapsulated in a glass tube.

摘要翻译： 其中将平板半导体和连接到半导体的前表面和后表面上的表面电极的引线和引线封装在玻璃管中的电子器件。

公开(公告)号：US07629667B2

公开(公告)日：2009-12-08

申请号：US10564885

申请日：2003-08-28

申请人： Mitsuo Usami

发明人： Mitsuo Usami

IPC分类号： H01L21/8222

CPC分类号： G06K19/07749 ,  G06K19/07775 ,  G06K19/07779 ,  G06K19/07783 ,  H01L23/5227 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3011 ,  H01Q1/22 ,  H01Q1/2283 ,  H01L2224/0401

摘要： An issue of reducing a product manufacture unit cost exists in wireless IC chips which are required to be disposable because the wireless IC chips circulate in a massive scale and require a very high collection cost. It is possible to increase the communication distance of a wireless IC chip with an on-chip antenna simply contrived for reduction of the production unit cost by increasing the size of the antenna mounted on a wireless IC chip or by increasing the output power of a reader as in a conventional way. However, because of the circumstances of the applications used and the read accuracy of the reader, the antenna cannot be mounted on a very small chip in an in-chip antenna form. When an AC magnetic field is applied to an on-chip antenna from outside, eddy current is produced in principle because the semiconductor substrate is conductive. It has been fount that the thickness of the substrate can be used as a design parameter because of the eddy current. Based on this finding, according to the invention, the thickness of the substrate is decreased to reduce or eliminate the energy loss due to the eddy current to utilize the electromagnetic wave energy for the semiconductor circuit operation as originally designed. With the thickness reduction, it is possible to increase the communication distance by preventing ineffective absorption of energy and thereby increasing the current flowing through the on-chip antenna.

摘要翻译： 由于无线IC芯片大量流通并且需要非常高的收集成本，所以无线IC芯片中存在降低产品制造单位成本的问题，这些无线IC芯片需要一次性使用。 可以通过增加安装在无线IC芯片上的天线的尺寸或通过增加读取器的输出功率来简单地设计用于降低生产单元成本的片上天线的无线IC芯片的通信距离 如常规方式。 然而，由于使用的应用环境和读取器的读取精度，天线不能以片内天线形式安装在非常小的芯片上。 当从外部向片上天线施加AC磁场时，由于半导体衬底是导电的，原则上产生涡电流。 由于涡电流，衬底的厚度可以用作设计参数。 基于这一发现，根据本发明，减小或消除了由于涡电流而导致的能量损耗，以便如最初设计的那样利用电磁波能量进行半导体电路操作。 通过减小厚度，可以通过防止能量的无效吸收从而增加流过片上天线的电流来增加通信距离。

公开(公告)号：US20090191668A1

公开(公告)日：2009-07-30

申请号：US12303066

申请日：2006-06-02

申请人： Mitsuo Usami

发明人： Mitsuo Usami

IPC分类号： H01L21/50

CPC分类号： H01L21/56 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： An IC tag inlet (100) is configured by: an upper side antenna (102) and a lower side antenna (103) sandwiching a semiconductor chip (101) that includes an upper electrode (132) and a lower electrode (133) from both upper and lower directions; and a support resin (104) covering the semiconductor chip (101). The semiconductor chip (101) is a micro chip having an outer size of 0.15 mm square or smaller, and a thickness of 10 μm or smaller. In a manufacturing process of the IC tag inlet (100), in order to make the handling of the semiconductor chip (101) easy, prior to a step of sandwiching the semiconductor chip (101) between the upper side antenna (102) and the lower side antenna (103), the whole surface of the semiconductor chip (101) is covered by the support resin (104), so that an effective volume is made large.

摘要翻译： IC标签入口（100）通过以下方式构成：上下侧天线（102）和下侧天线（103），其夹着半导体芯片（101），其包括来自两者的上电极（132）和下电极（133） 上下方向; 和覆盖半导体芯片（101）的支撑树脂（104）。 半导体芯片（101）是外形尺寸为0.15mm以下，厚度为10μm以下的微型芯片。 在IC标签入口（100）的制造过程中，为了使半导体芯片（101）的处理容易，在将半导体芯片（101）夹在上侧天线（102）和 下侧天线（103），半导体芯片（101）的整个表面被支撑树脂（104）覆盖，使得有效体积变大。