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    Semiconductor device using MIS capacitor
    1.
    发明授权
    Semiconductor device using MIS capacitor 失效
    半导体器件采用MIS电容器

    公开(公告)号：US5018000A

    公开(公告)日：1991-05-21

    申请号：US367046

    申请日：1989-06-16

    申请人： Toshio Yamada ,  Tohru Kobayashi ,  Hirotaka Nishizawa ,  Hiroyuki Itoh ,  Tatsuya Saitoh

    发明人： Toshio Yamada ,  Tohru Kobayashi ,  Hirotaka Nishizawa ,  Hiroyuki Itoh ,  Tatsuya Saitoh

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H03K17/60 ,  H03K19/003

    CPC分类号： H01L27/0647

    摘要： A MIS capacitor to be implemented in a semiconductor device employing various or predetermined circuits, has a dielectric side electrode which is in contact with a buried layer provided on a semiconductor substrate through a dielectric film and a buried layer-side electrode connected to the buried layer. The buried layer-side electrode of the MIS capacitor is connected to a low-impedance side of the circuit employed therewith. This structure, when connected as such, is capable of reducing the influence of noise attributed to an .alpha.-ray and thereby operating the circuit stably. The semiconductor device using a MIS capacitor invention is adaptable to an emitter follower circuit and various logic circuits for preventing malfunction resulting from .alpha.-ray radiation.

    摘要翻译： 在采用各种或预定电路的半导体器件中实现的MIS电容器具有通过电介质膜与设置在半导体衬底上的掩埋层接触的电介质侧电极和连接到掩埋层的掩埋层侧电极 。 MIS电容器的掩埋层侧电极与使用的电路的低阻抗侧连接。 当这样连接时，该结构能够减少归因于α射线的噪声的影响，从而稳定地操作电路。 使用MIS电容器发明的半导体器件适用于射极跟随器电路和用于防止由α射线辐射引起的故障的各种逻辑电路。

    Transistor circuit with improved .alpha. ray resistant properties
    2.
    发明授权
    Transistor circuit with improved .alpha. ray resistant properties 失效
    具有改进的抗α射线特性的晶体管电路

    公开(公告)号：US4942320A

    公开(公告)日：1990-07-17

    申请号：US208118

    申请日：1988-06-17

    申请人： Hiroyuki Itoh ,  Toshio Yamada ,  Akira Masaki ,  Tohru Kobayashi

    发明人： Hiroyuki Itoh ,  Toshio Yamada ,  Akira Masaki ,  Tohru Kobayashi

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/086

    CPC分类号： H03K17/16 ,  H03K19/0033 ,  H03K19/086

    摘要： A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit. It is disposed in a feedback part and used as a constant current source in a logic circuit comprising a logic part consisting of a differential transistor circuit and the feedback part for negatively feeding back the in-phase output of the differential transistor circuit.

    摘要翻译： 本发明的晶体管电路包括用于在其基极处接收第一偏压的第一晶体管，连接到第一晶体管的集电极的电阻器件和连接到第一晶体管和电阻器装置之间的结的钳位装置， 电阻器的端子与其与第一晶体管的连接相对。 当在第一晶体管中产生由于α射线引起的噪声电流并且输出降低时，钳位装置以使得电流流过钳位装置并防止输出变化的方式工作。 本发明的晶体管电路连接到电阻器或晶体管，并作为恒流电路用于向电阻器或晶体管提供电流，使得流过其中的电流恒定。 例如，它被用作射极跟随器的恒流源来构成电平移位电路。 它被布置在反馈部分中，并在逻辑电路中用作恒流源，该逻辑电路包括由差分晶体管电路和反馈部分组成的逻辑部分，用于对差分晶体管电路的同相输出进行负反馈。

    Flip-flop circuit
    3.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号：US4868420A

    公开(公告)日：1989-09-19

    申请号：US273729

    申请日：1988-11-18

    申请人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

    发明人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

    IPC分类号： H03K3/037 ,  H03K3/2885

    CPC分类号： H03K3/2885 ,  H03K3/0375

    摘要： An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.

    摘要翻译： 提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。 触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。 逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。 逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。 根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。

    Method of manufacturing a semiconductor integrated circuit device
    5.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US5342480A

    公开(公告)日：1994-08-30

    申请号：US069844

    申请日：1993-06-01

    申请人： Hirotaka Nishizawa ,  Seiichiro Azuma ,  Takayuki Yoshitake ,  Kazuo Tanaka ,  Mikinori Kawaji ,  Sinmei Hirano ,  Toshio Yamada ,  Yasusi Sekine

    发明人： Hirotaka Nishizawa ,  Seiichiro Azuma ,  Takayuki Yoshitake ,  Kazuo Tanaka ,  Mikinori Kawaji ,  Sinmei Hirano ,  Toshio Yamada ,  Yasusi Sekine

    IPC分类号： H01L21/265 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8248 ,  H01L27/108 ,  H01L27/12 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/786 ,  H01L21/306 ,  B44C1/22

    CPC分类号： H01L21/76229 ,  H01L21/8248 ,  H01L27/10829

    摘要： An isolation and flattening technique for a semiconductor substrate having active devices, such as a bipolar transistor, and a MISFET, formed thereon, is disclosed. The technique includes forming grooves, to the main surface of a non-active region of a semiconductor substrate or a semiconductor layer, each groove extending into the substrate or layer and forming island regions of the substrate or layer, forming a burying material and a first mask having an etching rate greater than that of the burying material successively over the entire surface of the semiconductor substrate or the semiconductor layer including areas on the upper surface of the island regions and in the grooves, such that the film thickness is made virtually uniform for each of the surfaces, forming a second mask on the surface of the first mask, through which the region on each of the island regions is exposed and in which the end of the opening is situated from the end of the island region to the outside of the island region within a distance 0.7 times of the film thickness for the sum of the burying material and the first mask, and applying isotropic etching successively to each of the first mask and the burying material by using the second mask as an etching mask, under a condition in which the etching rate for the first mask is greater than that for the burying material.

    摘要翻译： 公开了一种在其上形成有半导体衬底的隔离和平坦化技术，其具有诸如双极晶体管和MISFET之类的有源器件。 该技术包括在半导体衬底或半导体层的非有源区的主表面上形成凹槽，每个凹槽延伸到衬底或层中并形成衬底或层的岛区，形成掩埋材料和第一 在半导体衬底或半导体层的整个表面上连续地具有大于掩埋材料的蚀刻速率的掩模，该蚀刻速率包括在岛状区域和沟槽的上表面上的区域，使得膜厚实质上是均匀的 每个所述表面在所述第一掩模的表面上形成第二掩模，所述岛状区域中的所述区域通过所述第二掩模暴露，并且所述开口的所述端部从所述岛状区域的所述端部位于所述岛状区域的外部 在距离掩模材料和第一掩模的总和的膜厚的0.7倍的范围内的岛区域，并且将各向同性蚀刻连续地施加到e 在第一掩模的蚀刻速率大于掩埋材料的蚀刻速率的条件下，通过使用第二掩模作为蚀刻掩模，在第一掩模和掩埋材料的掩模之间。

    Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions
    6.
    发明授权
    Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
    具有多个具有主动下拉功能的逻辑电路的半导体集成电路器件

    公开(公告)号：US5298802A

    公开(公告)日：1994-03-29

    申请号：US56798

    申请日：1993-05-03

    申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

    发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

    IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

    摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

    摘要翻译： 根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。 射极跟随器输出电路由相位分离电路的反相输出驱动。 同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动 电路。 作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。 输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。 由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。 在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。 此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

    Integrated logic circuit
    8.
    发明授权
    Integrated logic circuit 失效
    集成逻辑电路

    公开(公告)号：US5059819A

    公开(公告)日：1991-10-22

    申请号：US133915

    申请日：1987-12-16

    申请人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

    发明人： Kazuo Tanaka ,  Masato Hamamoto ,  Toshio Yamada ,  Tohru Kobayashi ,  Hiromasa Katoh

    IPC分类号： G01R31/3185 ,  H01L27/02

    CPC分类号： H01L27/0207 ,  G01R31/318538 ,  G01R31/318572

    摘要： Flip-flops are disposed corresponding to input circuits or output circuits of an integrated logic circuit so as to be cascaded to configure a shift register for a test and to enable a parallel transfer of data between each flip-flop and a corresponding input or output circuit. As a result, without connecting the probe to all terminals of the LSI, test signals can be supplied from some terminals via all input circuits to an internal circuit so as to conduct a diagnosis.

    摘要翻译： 触发器对应于集成逻辑电路的输入电路或输出电路进行布置，以便级联以配置用于测试的移位寄存器，并且能够在每个触发器和相应的输入或输出电路之间并行传输数据 。 结果，在不将探头连接到LSI的所有端子的情况下，可以通过所有输入电路从一些端子向内部电路提供测试信号，以进行诊断。