公开(公告)号：US07652606B2

公开(公告)日：2010-01-26

申请号：US12048309

申请日：2008-03-14

申请人： Shogo Itoh ,  Hisao Suzuki

发明人： Shogo Itoh ,  Hisao Suzuki

IPC分类号： H03M1/66

CPC分类号： H03M1/0863 ,  H03M1/765

摘要： A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

摘要翻译： 一种数模转换器，包括彼此耦合并且连接到高电位电源的开关元件的第一选择电路和开关元件的第二选择电路，它们彼此耦合并且连接到低电位电源 。 第一和第二分压电路各自包括串联连接的电阻器元件，每个电阻元件耦合在相应选择电路的相邻开关元件之间。 控制电路向选择电路提供控制信号以激活每个选择电路中的一个开关元件，并将激活的开关元件耦合到相应的电位电源。 第一和第二分压电路将高电位和低电位电源的电压与激活的开关元件之间的电阻元件分开。

公开(公告)号：US06788239B2

公开(公告)日：2004-09-07

申请号：US10426636

申请日：2003-05-01

申请人： Hisao Suzuki ,  Shogo Itoh

发明人： Hisao Suzuki ,  Shogo Itoh

IPC分类号： H03M136

CPC分类号： H03M1/0604 ,  H03M1/002 ,  H03M1/36

摘要： It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

摘要翻译： 旨在提供一种A / D转换器电路，通过使用时钟信号，通过输入预定时间过去的模拟电压，可以选择要被操作的适当的比较器和待休止的比较器，以及 功耗小。 并行型A / D转换器电路200通过使用斩波型比较器1-7的时钟信号CLK将模拟电压VIN以预定周期的间隔转换为数字值DOUT。 比较器1-7可以由第一和第二设置信号CONT1A等设置为操作状态和静止状态中的任一个。 比较器控制电路部分211在前一转换中对比较器输出端OUT1-OUT7执行逻辑处理，以产生第一和第二设置信号CONT1A等，并使一些比较器进入运行状态并将其余的比较器保持在休眠状态 州。

公开(公告)号：US08310306B2

公开(公告)日：2012-11-13

申请号：US12796500

申请日：2010-06-08

申请人： Shogo Itoh ,  Hisao Suzuki

发明人： Shogo Itoh ,  Hisao Suzuki

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2203/45646 ,  H03F2203/45652

摘要： An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

摘要翻译： 运算放大器包括施加输入信号的第一放大器和施加第一放大器的输出的第二放大器，其中第二放大器包括第一晶体管，第一晶体管包括第一放大器的输出为第 以及包括施加了第一放大器的输出的栅极的第二晶体管和耦合到第一晶体管的源极的漏极。

公开(公告)号：US06985095B2

公开(公告)日：2006-01-10

申请号：US10890412

申请日：2004-07-14

申请人： Hisao Suzuki ,  Shogo Itoh

发明人： Hisao Suzuki ,  Shogo Itoh

IPC分类号： H03M1/36 ,  G05F1/10

CPC分类号： H03M1/0604 ,  H03M1/002 ,  H03M1/36

摘要： It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1–7. The comparators 1–7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1–OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

摘要翻译： 旨在提供一种A / D转换器电路，通过使用时钟信号，通过输入预定时间过去的模拟电压，可以选择要被操作的适当的比较器和待休止的比较器，以及 功耗小。 并行型A / D转换器电路200通过使用斩波型比较器1-7的时钟信号CLK将模拟电压VIN以预定周期的间隔转换为数字值DOUT。 比较器1-7可以通过第一和第二设置信号CONT 1A等设置为操作状态和静止状态中的任一个。 比较器控制电路部分211在前一转换中对比较器输出端OUT 1 -OUT 7执行逻辑处理，以产生第一和第二设置信号CONT 1A等，并使一些比较器保持在运行状态并保持其余的 比较者处于休息状态。

公开(公告)号：US20100308913A1

公开(公告)日：2010-12-09

申请号：US12796500

申请日：2010-06-08

申请人： Shogo ITOH ,  Hisao Suzuki

发明人： Shogo ITOH ,  Hisao Suzuki

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2203/45646 ,  H03F2203/45652

摘要： An operational amplifier includes a first amplifier to which an input signal is applied, and a second amplifier to which an output of the first amplifier is applied, wherein the second amplifier includes a first transistor including a gate to which the output of the first amplifier is applied, and a second transistor including a gate to which the output of the first amplifier is applied, and a drain coupled to a source of the first transistor.

摘要翻译： 运算放大器包括施加输入信号的第一放大器和施加第一放大器的输出的第二放大器，其中第二放大器包括第一晶体管，第一晶体管包括第一放大器的输出为第 以及包括施加了第一放大器的输出的栅极的第二晶体管和耦合到第一晶体管的源极的漏极。

公开(公告)号：US20050052308A1

公开(公告)日：2005-03-10

申请号：US10890412

申请日：2004-07-14

申请人： Hisao Suzuki ,  Shogo Itoh

发明人： Hisao Suzuki ,  Shogo Itoh

IPC分类号： H03M1/00 ,  H03M1/36

CPC分类号： H03M1/0604 ,  H03M1/002 ,  H03M1/36

摘要： It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONTLA etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

摘要翻译： 旨在提供一种A / D转换器电路，通过使用时钟信号，通过输入预定时间过去的模拟电压，可以选择要被操作的适当的比较器和待休止的比较器，以及 功耗小。 并行型A / D转换器电路200通过使用斩波型比较器1-7的时钟信号CLK将模拟电压VIN以预定周期的间隔转换为数字值DOUT。 比较器1-7可以由第一和第二设置信号CONT1A等设置为操作状态和静止状态中的任一个。 比较器控制电路部分211在前一转换中对比较器输出端OUT1-OUT7执行逻辑处理，以产生第一和第二设置信号CONTLA等，并使一些比较器进入运行状态并将剩余的比较器保持在休眠状态 州。

公开(公告)号：US20080224909A1

公开(公告)日：2008-09-18

申请号：US12048309

申请日：2008-03-14

申请人： Shogo Itoh ,  Hisao Suzuki

发明人： Shogo Itoh ,  Hisao Suzuki

IPC分类号： H03M1/66

CPC分类号： H03M1/0863 ,  H03M1/765

摘要： A digital-analog converter including a first selection circuit of switch elements, which are coupled to each other and to a high potential power supply, and a second selection circuit of switch elements, which are coupled to each other and to a low potential power supply. First and second voltage dividing circuit each include series-connected resistor elements, each coupled between adjacent switch elements of the corresponding selection circuit. A control circuit provides a control signal to the selection circuits to activate one of the switch elements in each selection circuit and couple the activated switch element to the corresponding potential power supply. The first and second voltage dividing circuits divide voltages of the high and low potential power supplies with the resistor elements between the activated switch elements.

摘要翻译： 一种数模转换器，包括彼此耦合并且连接到高电位电源的开关元件的第一选择电路和开关元件的第二选择电路，它们彼此耦合并且连接到低电位电源 。 第一和第二分压电路各自包括串联连接的电阻器元件，每个电阻元件耦合在相应选择电路的相邻开关元件之间。 控制电路向选择电路提供控制信号以激活每个选择电路中的一个开关元件，并将激活的开关元件耦合到相应的电位电源。 第一和第二分压电路将高电位和低电位电源的电压与激活的开关元件之间的电阻元件分开。

公开(公告)号：US08895110B2

公开(公告)日：2014-11-25

申请号：US13402136

申请日：2012-02-22

申请人： Hidemitsu Takaoka ,  Akira Osada ,  Naoki Wakiya ,  Hisao Suzuki ,  Kazuo Shinozaki

发明人： Hidemitsu Takaoka ,  Akira Osada ,  Naoki Wakiya ,  Hisao Suzuki ,  Kazuo Shinozaki

IPC分类号： B05D3/02 ,  B05D3/10 ,  C23C18/12 ,  C23C28/04

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1254 ,  C23C18/127 ,  C23C18/1283 ,  C23C18/1295 ,  C23C28/044 ,  C23C30/005

摘要： A method of manufacturing a surface-coated cutting tool includes: forming an aluminum oxide layer having a layer thickness of 0.05 to 5 μm and an α-alumina structure with a corundum type crystal structure on a cutting tool body using a sol-gel method. The step of forming includes adding an alcohol to aluminum alkoxide; adding an acid; stirring the mixture at 10° C. or lower to form a sol; applying the sol on a surface of the cutting tool body or an outer-most surface of a hard-coating layer formed on the surface of the cutting tool body; performing a drying process at least once, the applied sol being dried at 100 to 400° C. in the drying process; and annealing the cutting tool body with a dried sol layer at 500 to 1000° C.

摘要翻译： 表面涂层切削工具的制造方法包括：使用溶胶 - 凝胶法在切削工具主体上形成层厚度为0.05〜5μm的氧化铝层和刚玉型结晶结构的α-氧化铝结构体。 成型步骤包括向醇中加入醇; 加酸 在10℃以下搅拌该混合物以形成溶胶; 将所述溶胶涂布在所述切削工具主体的表面上，或者形成在所述切削工具主体的表面上的硬涂层的最外表面; 至少进行一次干燥处理，在干燥工序中，将涂布的溶胶在100〜400℃干燥; 并在500〜1000℃下用干燥的溶胶层退火切削工具主体。

公开(公告)号：US08884499B2

公开(公告)日：2014-11-11

申请号：US14125520

申请日：2012-08-06

申请人： Toshinari Noda ,  Takashi Kubo ,  Hisao Suzuki ,  Naoki Wakiya ,  Naonori Sakamoto

发明人： Toshinari Noda ,  Takashi Kubo ,  Hisao Suzuki ,  Naoki Wakiya ,  Naonori Sakamoto

IPC分类号： H01L41/047 ,  H01L41/08 ,  H01L41/187

CPC分类号： H01L41/047 ,  H01L41/0478 ,  H01L41/081 ,  H01L41/0815 ,  H01L41/1876

摘要： A piezoelectric element includes a substrate, a lower electrode layer, a piezoelectric layer, and an upper electrode layer. The lower electrode layer is fixed to the substrate and the piezoelectric layer is formed on the lower electrode layer. The upper electrode layer is formed on piezoelectric layer. The lower electrode layer contains pores therein and has a larger thermal expansion coefficient than the piezoelectric layer.

摘要翻译： 压电元件包括​​基板，下电极层，压电层和上电极层。 下电极层固定在基板上，压电层形成在下电极层上。 上电极层形成在压电层上。 下电极层在其中含有孔，并且具有比压电层更大的热膨胀系数。

公开(公告)号：US20120219720A1

公开(公告)日：2012-08-30

申请号：US13402136

申请日：2012-02-22

申请人： Hidemitsu TAKAOKA ,  Akira Osada ,  Naoki Wakiya ,  Hisao Suzuki ,  Kazuo Shinozaki

发明人： Hidemitsu TAKAOKA ,  Akira Osada ,  Naoki Wakiya ,  Hisao Suzuki ,  Kazuo Shinozaki

IPC分类号： B05D3/02

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1254 ,  C23C18/127 ,  C23C18/1283 ,  C23C18/1295 ,  C23C28/044 ,  C23C30/005

摘要： A method of manufacturing a surface-coated cutting tool includes: forming an aluminum oxide layer having a layer thickness of 0.05 to 5 μm and an α-alumina structure with a corundum type crystal structure on a cutting tool body using a sol-gel method. The step of forming includes adding an alcohol to aluminum alkoxide; adding an acid; stirring the mixture at 10° C. or lower to form a sol; applying the sol on a surface of the cutting tool body or an outer-most surface of a hard-coating layer formed on the surface of the cutting tool body; performing a drying process at least once, the applied sol being dried at 100 to 400° C. in the drying process; and annealing the cutting tool body with a dried sol layer at 500 to 1000° C.

摘要翻译： 表面涂层切削工具的制造方法包括：使用溶胶 - 凝胶法在切削工具主体上形成层厚度为0.05〜5μm的氧化铝层和刚玉型结晶结构的α-氧化铝结构体。 成型步骤包括向醇中加入醇; 加酸 在10℃以下搅拌该混合物以形成溶胶; 将所述溶胶涂布在所述切削工具主体的表面上，或者形成在所述切削工具主体的表面上的硬涂层的最外表面; 至少进行一次干燥处理，在干燥工序中，将涂布的溶胶在100〜400℃干燥; 并在500〜1000℃下用干燥的溶胶层退火切削工具主体。