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公开(公告)号：US10679103B2
公开(公告)日：2020-06-09
申请号：US15992246
申请日：2018-05-30
Applicant: Hitachi, Ltd.
Inventor： Yuki Kondo , Katsuto Sato
Abstract: Provided is an information processing apparatus configured to convert image data that has been input into saved data to save in a storage unit and reproduce the image data from the saved data. The information processing apparatus includes: an encoder unit configured to convert the image data into the saved data; and a decoder unit configured to reproduce the saved data as the image data. The encoder unit includes: a recognition unit configured to generate class tag information from the image data that has been input; a segmentation unit configured to generate region information that distinguishes a recognition target region and a background region from the image data that has been input; and a region separation unit configured to generate a background image according to the background region from the image data that has been input based on the region information.
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公开(公告)号：US09461962B2
公开(公告)日：2016-10-04
申请号：US14562139
申请日：2014-12-05
Applicant: Hitachi, Ltd.
Inventor： Katsuto Sato , Junji Yamamoto
CPC classification number: H04L61/2038 , G06F13/4022 , G06F13/4221 , H04L41/0806 , H04L61/6045
Abstract: A network address management unit (210) allocates, to the first edge node, a first network address (500) on which a physical configuration of a first edge node (100a) is reflected. The network address management unit, when a second edge node (100b) is coupled to the first edge node, allocates, to the first edge node, a second network address (510) on which the physical configuration of the first edge node is reflected with respect to the second edge node. When the first edge node receives a packet that designates the first or second network address as a destination network address, the first edge node, based on the destination network address designated by the received packet, determines whether the received packet is transferred to the second edge node and discriminates a transfer destination path in the first edge node.
Abstract translation: 网络地址管理单元（210）向第一边缘节点分配反映第一边缘节点（100a）的物理配置的第一网络地址（500）。 网络地址管理单元，当第二边缘节点（100b）耦合到第一边缘节点时，向第一边缘节点分配第二网络地址（510），第一边缘节点的物理配置被反映在其上 相对于第二边缘节点。 当第一边缘节点接收到指定第一或第二网络地址作为目的地网络地址的分组时，第一边缘节点基于由接收到的分组指定的目的地网络地址来确定所接收的分组是否被传送到第二边缘 并且识别第一边缘节点中的传送目的地路径。
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公开(公告)号：US11662953B2
公开(公告)日：2023-05-30
申请号：US17481130
申请日：2021-09-21
Applicant: Hitachi, Ltd.
Inventor： Katsuto Sato , Hiroaki Akutsu , Akifumi Suzuki , Takahiro Naruko
CPC classification number: G06F3/0661 , G06F3/067 , G06F3/0608 , H03M7/30
Abstract: To provide a data compression/decompression system that can appropriately decompress compressed data.
A first computer generates first identification information that can identify a first execution environment; and stores the first identification information on a storage device in association with compressed data of data. A second computer generates second identification information that can identify a second execution environment; and determines whether or not the first identification information, and the second identification information match. In a case that it is determined that the first identification information, and the second identification information do not match, the second computer requests a third computer that is capable of decompression of the compressed data to decompress the compressed data, the third computer decompresses the compressed data, and transmits decompressed data to the second computer, and the second computer completes the decompression of the compressed data by receiving the decompressed data from the third computer.-
公开(公告)号：US20220374156A1
公开(公告)日：2022-11-24
申请号：US17642843
申请日：2021-03-04
Applicant: Hitachi, Ltd.
Inventor： Takahiro Naruko , Hiroaki Akutsu , Akifumi Suzuki , Katsuto Sato
IPC: G06F3/06
Abstract: Provided is a data processing system which includes a processor and a storage device, and inputs/outputs data using a learned compander that compresses and expands data, wherein the data processing system comprises an estimation unit which uses learning data and estimates a region of interest to a data model, and a learning unit which causes the compander to learn according to an evaluation function in which each region was weighted based on the region of interest, and a result of the compander compressing and expanding the learning data.
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Patent Agency Ranking
公开(公告)号：US10592274B2
公开(公告)日：2020-03-17
申请号：US15755441
申请日：2015-10-26
Applicant: HITACHI, LTD.
Inventor： Katsuto Sato , Tetsuro Honmura
Abstract: This computer system includes: at least one computer having a memory and a plurality of CPU cores; and a storage sub device having a plurality of logical storage units configured using storage devices. In the computer, a plurality of queues are configured in the memory, and at least one of the plurality of CPU cores is assigned to each of the plurality of queues. The queue is enqueued with an I/O command dispatched from a CPU core, to which the queue is assigned, to a logical storage unit. The computer system has access control information including information concerning whether to accept or refuse access from each queue to each logical storage unit.
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公开(公告)号：US10162530B2
公开(公告)日：2018-12-25
申请号：US15126672
申请日：2014-09-18
Applicant: Hitachi, Ltd.
Inventor： Katsuto Sato , Yuki Kondoh
IPC: G06F3/06
Abstract: A computer coupled to an external apparatus via an I/O device comprising, a control unit configured to assign a command identifier to a command issued to the external apparatus, wherein the I/O device includes a collision detection unit defined a partial command identifier space which is a subspace of a command identifier space that is a set of a plurality of command identifiers, and wherein the collision detection unit is configured to: shift an arrangement of the partial command identifier space within the command identifier space; and determine whether or not the assigned command identifier collides with another command identifier that is in use.
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公开(公告)号：US11842055B2
公开(公告)日：2023-12-12
申请号：US17642843
申请日：2021-03-04
Applicant: Hitachi, Ltd.
Inventor： Takahiro Naruko , Hiroaki Akutsu , Akifumi Suzuki , Katsuto Sato
IPC: G06F3/06
CPC classification number: G06F3/0626 , G06F3/0629 , G06F3/0673
Abstract: Provided is a data processing system which includes a processor and a storage device, and inputs/outputs data using a learned compander that compresses and expands data, wherein the data processing system comprises an estimation unit which uses learning data and estimates a region of interest to a data model, and a learning unit which causes the compander to learn according to an evaluation function in which each region was weighted based on the region of interest, and a result of the compander compressing and expanding the learning data.
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公开(公告)号：US10481946B2
公开(公告)日：2019-11-19
申请号：US15124883
申请日：2014-05-12
Applicant: HITACHI, LTD.
Inventor： Katsuto Sato , Yuki Kondo
Abstract: An information processing device for reducing the number of times of interrupt notification for notifying completion of execution of input/output instruction and lightening a load of interrupt processing is described. The information processing device prescribes that a driver checks a completion state of a preceding input/output instruction after issuance of the input/output instruction. An issuing timing of the input/output instruction is considered to be a polling timing for checking the completion state of the preceding input/output instruction. Before the input/output device transmits interrupt notification to a CPU, the input/output device sets a timer to stand by for a prescribed time. A processing unit which resets the timer and extends the standby time by a prescribed time in a case where notification that a subsequent input/output instruction is issued arrives from a driver to the input/output device during the time is additionally provided to the input/output device.
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公开(公告)号：US10402333B2
公开(公告)日：2019-09-03
申请号：US15769348
申请日：2016-01-18
Applicant: Hitachi, Ltd.
Inventor： Katsuto Sato , Nobukazu Kondo , Naruki Kurata
IPC: G06F12/08 , G06F12/0862 , G06F12/10 , G06F12/1009 , G06F12/109
Abstract: A computer system includes a main memory, a lower class memory, and a secondary storage medium and executes an operating system, an in-memory computing program, and a prefetch optimizer program. The in-memory computing program writes processing target data including a plurality of data objects stored in the secondary storage medium into a plurality of continuous areas on a virtual memory space and executes a process while accessing the continuous area. When detecting that the operating system executes a class-in process triggered upon a page fault for a predetermined virtual page, the prefetch optimizer program acquires information of the continuous area from the in-memory computing program and directs the operating system to execute a class-in process for virtual pages included in the predetermined continuous area including the predetermined virtual page.
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