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公开(公告)号：US20180365605A1
公开(公告)日：2018-12-20
申请号：US15921750
申请日：2018-03-15
Applicant: Hitachi, Ltd.
Inventor： Yoshiki KUROKAWA , Hiroki MIYAMOTO , Yoshiteru TAKESHIMA , Toshihiko KASHIYAMA
Abstract: To shorten the simulation time without deteriorating the simulation accuracy. In a supply chain simulation system which performs simulation of a supply chain, a simulation data dividing unit creates a plurality of simulation divided input data obtained by consolidating and classifying, based on the transport-related information of each of the divided groups, simulation input data related to products of the plurality of items for each item in which the transport-related information of each of the divided groups are closely related to each other, and a plurality of simulators individually execute division simulation based on the plurality of simulation divided input data.
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公开(公告)号：US20170124077A1
公开(公告)日：2017-05-04
申请号：US15129489
申请日：2014-04-24
Applicant: Hitachi, Ltd.
Inventor： Satoru WATANABE , Akira YAMAMOTO , Yoshiki KUROKAWA , Yoshitaka TSUJIMOTO
IPC: G06F17/30 , G06F12/0802 , G06F12/1009 , G06F3/06
CPC classification number: G06F16/24552 , G06F3/061 , G06F3/0611 , G06F3/0644 , G06F3/0659 , G06F3/0688 , G06F12/0802 , G06F12/0868 , G06F12/1009 , G06F2212/222 , G06F2212/465 , G06F2212/60 , G06F2212/7201
Abstract: A storage apparatus to be coupled to a network, the storage apparatus comprising: a controller; and a storage medium to be coupled to the controller, the storage medium comprising one or more flash modules each comprising a database operation module, the controller being configured to receive a database operation command, and to cause the one or more flash modules to execute the received database operation command.
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公开(公告)号：US20210125103A1
公开(公告)日：2021-04-29
申请号：US17071025
申请日：2020-10-15
Applicant: Hitachi, Ltd.
Inventor： Yuichiro AOKI , Yuki KONDO , Yoshiki KUROKAWA
Abstract: A computer system executing a learning process for generating a model includes: a computer having calculation cores; and a learning section. The learning section acquires performance information indicating performance characteristics of the calculation cores executing a positive sample calculation and the calculation cores executing a negative sample calculation, computes a maximum value of the number of negative samples in the negative sample calculation on the basis of the performance information, determines the number of the negative samples based on the maximum value, and generates the model by causing at least one of the calculation cores to execute the positive sample calculation using a predetermined number of pieces of training data to serve as positive samples in the training data, and by causing at least one of the calculation cores to execute the negative sample calculation using the determined number of the negative samples randomly selected from the training data.
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公开(公告)号：US20190180223A1
公开(公告)日：2019-06-13
申请号：US16122365
申请日：2018-09-05
Applicant: HITACHI, LTD.
Inventor： Yoshiteru TAKESHIMA , Hiroki MIYAMOTO , Yoshiki KUROKAWA
IPC: G06Q10/08
Abstract: A supply chain model generation system independently uses a business entity code and an item code representing an item related to a transaction in result information on a supply chain operation of a plurality of business entities; transaction information is extracted from the result information and a transaction time series information table is generated; a relationship in the transaction time series information table in each business entity is analyzed and a virtual business entity code on a supply side and a virtual business entity code on a demand side are assigned for each business entity code; and further a logical model information table where a virtual item code is assigned with respect to an item code related to the transaction of a business entity of the virtual business entity code on the supply side and a business entity of the virtual business entity code on the demand side is generated.
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公开(公告)号：US20180165148A1
公开(公告)日：2018-06-14
申请号：US15571050
申请日：2015-06-29
Applicant: Hitachi, Ltd.
Inventor： Satoru WATANABE , Yoshiki KUROKAWA , Yoshitaka TSUJIMOTO
CPC classification number: G06F11/1004 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F16/00 , G06F16/2455
Abstract: A computer including a processor and a memory and a storage device that is connected to the computer and stores data has an FPGA that acquires data and an operation command from a control unit that controls reading and writing with respect to a non-volatile semiconductor storage unit to perform a data operation. The computer generates and transmits the operation command from an access request that has been received to the storage device. The computer receives execution results for the operation command from the storage device, and when the number of execution results for the operation command reaches a prescribed value, instructs the FPGA to detect a soft error, receives all execution results with respect to the generated operation command, and if there is no soft error, transmits the execution results.
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Patent Agency Ranking
公开(公告)号：US20170286458A1
公开(公告)日：2017-10-05
申请号：US15510756
申请日：2015-02-25
Applicant: Hitachi, Ltd.
Inventor： Satoru WATANABE , Yoshiki KUROKAWA , Yoshitaka TSUJIMOTO
IPC: G06F17/30
CPC classification number: G06F16/217 , G06F16/00 , G06F16/24542 , G06F16/90335
Abstract: A computer comprising a processor and a memory and providing a database management unit for managing a database, said computer having a device that is connected to the processor via an interface and that comprises: at least one nonvolatile semiconductor storage device which has a plurality of nonvolatile semiconductor memories and which stores a database; at least one database calculation module which reads the database from the nonvolatile semiconductor storage device and performs calculations in the database; and a switch which connects the interface to the nonvolatile semiconductor storage device and the database calculation module.
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公开(公告)号：US20170192718A1
公开(公告)日：2017-07-06
申请号：US15126693
申请日：2014-04-28
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka TSUJIMOTO , Satoru WATANABE , Yoshiki KUROKAWA , Mitsuhiro OKADA , Akifumi SUZUKI
CPC classification number: G06F3/0659 , G06F3/061 , G06F3/0656 , G06F3/0658 , G06F3/0688 , G06F11/1044 , G06F12/00
Abstract: A storage apparatus has a plurality of hardware engines which send and receive information to and from a controller, which, on the condition of acquiring a request command from a host, determines identifying information of the request command, executes data I/O processing to the storage device according to the request command when first identifying information has been added to the request command and when second identifying information has been added to the acquired request command, transfers the request command to the hardware engine, acquires the data requested by the hardware engine from the storage device and transfers the acquired data to the hardware engine. The hardware engine acquires and analyzes an add-on command from the host and according to the request command, requests the controller to transfer the data based on the analysis result, and thereafter executes processing to the data transferred by the controller according to the add-on command.
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8.发明公开公开(公告)号：US20230378806A1
公开(公告)日：2023-11-23
申请号：US18030862
申请日：2021-10-14
Applicant: Hitachi, Ltd.
Inventor： Tsubasa ICHIKAWA , Shinya SUENAGA , Yasuyuki TADA , Yasushi MIYATA , Yoshiki KUROKAWA
CPC classification number: H02J13/00034 , H02J3/0073 , H02J3/0012
Abstract: Disclosed is a system for supporting creation of a system plan to change a configuration of a power system including a power transmission system and a power distribution system. The system stores information on a configuration of the power transmission system and information on a configuration and a load of the power distribution system. The system determines, based on the information on the configuration and the load of the power distribution system, a load accommodation capacity between power distribution substations which indicates a power supply capacity allowed to be compensated for between the power distribution substations through a configuration change of the power distribution system. The system creates a system plan proposal including a change in system configuration of the power transmission system and the power distribution system based on the load accommodation capacity. The system outputs information on the system plan proposal to an output device.
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公开(公告)号：US20170017395A1
公开(公告)日：2017-01-19
申请号：US15124690
申请日：2014-03-27
Applicant: HITACHI, LTD.
Inventor： Yoshiki KUROKAWA , Satoru WATANABE , Yoshitaka TSUJIMOTO , Mitsuhiro OKADA , Akifumi SUZUKI
Abstract: A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.
Abstract translation: 管理控制器控制数据缓冲器和闪存控制器，其基于搜索请求来控制到闪速存储器的数据的I / O。 数据解压缩引擎包括用于并行地解压缩从数据缓冲器传送的压缩数据的多个数据解压缩电路。 数据搜索引擎包括多个数据搜索电路，用于并行搜索满足由数据解压缩电路解压缩的各个数据之中的搜索条件的数据，并将搜索请求源传送到搜索中获得的数据 由数据搜索电路执行，其中闪存控制器并行地读取在搜索请求中请求的多个压缩数据，并将读取的压缩数据传送到数据缓冲器，并且管理控制器将压缩数据传送到数据解压缩 引擎当压缩数据存储在数据缓冲区中时。
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公开(公告)号：US20250110659A1
公开(公告)日：2025-04-03
申请号：US18830800
申请日：2024-09-11
Applicant: Hitachi, Ltd.
Inventor： Mayuko OZAWA , Norifumi NISHIKAWA , Yoshiki KUROKAWA , Kazuhiko MOGI
IPC: G06F3/06
Abstract: A data processing apparatus has a memory and a first storage apparatus and reads a data area from a second storage apparatus (a storage apparatus which is slower than the first storage apparatus and stores a plurality of data areas as data constituent elements). Regarding each processing block, the data processing apparatus determines whether an open/closed area for processing of a first processing block which is the processing block should be an entire area or a partial area of the data area, based on whether or not the data area which is input and/or output by the processing of the first processing block can also be accessed by processing of a second processing block which is a processing block other than the first processing block, and whether or not the second processing block is being executed.
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