公开(公告)号：US08760924B2

公开(公告)日：2014-06-24

申请号：US13427263

申请日：2012-03-22

申请人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

发明人： Hitoshi Iwai ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

IPC分类号： G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

公开(公告)号：US20130021848A1

公开(公告)日：2013-01-24

申请号：US13427263

申请日：2012-03-22

申请人： Hitoshi IWAI ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

发明人： Hitoshi IWAI ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Masaru Kito

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/06

摘要： A memory cell comprises a first semiconductor layer, and a first conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a semiconductor substrate. The first conductive layer sandwiches a charge storage layer with the first semiconductor layer. A control circuit executes a first program operation and then executes a second program operation. The first program operation supplies a first voltage to the body of the memory cell and supplies a second voltage larger than the first voltage to the gate of the memory cell. The second program operation renders the body of the memory cell in a floating state and supplies a third voltage which is positive to the gate of the memory cell.

摘要翻译： 存储单元包括第一半导体层和第一导电层。 第一半导体层相对于半导体衬底在垂直方向上延伸。 第一导电层与第一半导体层夹着电荷存储层。 控制电路执行第一程序操作，然后执行第二程序操作。 第一编程操作向存储单元的主体提供第一电压，并将大于第一电压的第二电压提供给存储单元的栅极。 第二程序操作使存储器单元的主体呈浮置状态，并向存储器单元的栅极提供为正的第三电压。

公开(公告)号：US20120132981A1

公开(公告)日：2012-05-31

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US20110018050A1

公开(公告)日：2011-01-27

申请号：US12727830

申请日：2010-03-19

申请人： Tomoko FUJIWARA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko FUJIWARA ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/51 ,  H01L21/4763

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。 连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

公开(公告)号：US09025377B2

公开(公告)日：2015-05-05

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C16/22 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US08767452B2

公开(公告)日：2014-07-01

申请号：US13418651

申请日：2012-03-13

申请人： Masaru Kito ,  Tomoko Fujiwara ,  Hideaki Aochi

发明人： Masaru Kito ,  Tomoko Fujiwara ,  Hideaki Aochi

IPC分类号： G11C11/14 ,  G11C11/00

CPC分类号： H01L27/11565 ,  G11C5/025 ,  H01L27/11582 ,  H01L29/7926

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, a charge storage layer, a tunneling layer, a dividing trench and a first heating unit. The stacked body includes a plurality of first insulating films stacked alternately with a plurality of electrode films. The semiconductor pillar pierces the stacked body. The charge storage layer is provided between the electrode films and the semiconductor pillar. The tunneling layer is provided between the charge storage layer and the semiconductor pillar. The dividing trench is provided between the semiconductor pillars in one direction orthogonal to a stacking direction of the stacked body to divide the electrode films. The first heating unit is provided in an interior of the dividing trench.

摘要翻译： 根据一个实施例，半导体存储器件包括堆叠体，半导体柱，电荷存储层，隧道层，分隔沟槽和第一加热单元。 层叠体包括与多个电极膜交替堆叠的多个第一绝缘膜。 半导体柱穿透层叠体。 电荷存储层设置在电极膜和半导体柱之间。 隧道层设置在电荷存储层和半导体柱之间。 在与层叠体的堆叠方向正交的一个方向上的半导体柱之间设置分割沟槽，以分割电极膜。 第一加热单元设置在分隔沟槽的内部。

公开(公告)号：US08766351B2

公开(公告)日：2014-07-01

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US08436414B2

公开(公告)日：2013-05-07

申请号：US12706127

申请日：2010-02-16

申请人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

发明人： Hiroyasu Tanaka ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Junya Matsunami ,  Ryouhei Kirisawa

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.

摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

公开(公告)号：US08189371B2

公开(公告)日：2012-05-29

申请号：US12851002

申请日：2010-08-05

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C11/14

CPC分类号： G11C16/0483 ,  G11C16/06 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括层叠体，通孔，半导体柱和电荷存储膜。 层叠体包括交替层叠有多个电极膜的多个绝缘膜。 通孔形成在堆叠体中以沿堆叠方向对齐。 半导体柱埋在通孔中。 电荷存储膜设置在电极膜和半导体柱之间。 在电极膜和半导体柱之间的每个交叉处形成存储单元。 控制电路将第一值写入至少部分存储单元，从写入第一值的存储单元执行第一值的擦除操作，读取存储在经过擦除操作的存储单元中的数据，并将 在从存储器单元读取第一值的情况下，存储器单元不可用。

公开(公告)号：US08188530B2

公开(公告)日：2012-05-29

申请号：US12728727

申请日：2010-03-22

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L21/8239 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.

摘要翻译： 一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上​​半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。