公开(公告)号：US4633438A

公开(公告)日：1986-12-30

申请号：US681027

申请日：1984-12-13

申请人： Hitoshi Kume ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Toru Kaga ,  Yasuo Igura ,  Akihiro Shimizu

发明人： Hitoshi Kume ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Toru Kaga ,  Yasuo Igura ,  Akihiro Shimizu

IPC分类号： G11C11/405 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

CPC分类号： G11C11/405 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108

摘要： In a 3-transistor random access memory for dynamic operation, the invention discloses a structure in which one of the transistors is stacked on the other transistor. A transistor for writing is disposed on a transistor for reading, and one of its terminals is used in common with the gate electrode of a transistor for judging data. The other terminal is connected to one of the terminals of the transistor for reading.A memory cell capable of extremely large scale integration can be obtained.

摘要翻译： 在用于动态操作的3晶体管随机存取存储器中，本发明公开了一种晶体管中的一个堆叠在另一个晶体管上的结构。 用于写入的晶体管设置在用于读取的晶体管上，并且其一个端子与用于判断数据的晶体管的栅电极共同使用。 另一个端子连接到晶体管的一个端子用于读取。 可以获得能够进行极大规模集成的存储单元。

公开(公告)号：US4668970A

公开(公告)日：1987-05-26

申请号：US803789

申请日：1985-12-02

申请人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Shinichi Minami ,  Toru Kaga

发明人： Yuji Yatsuda ,  Takaaki Hagiwara ,  Masatada Horiuchi ,  Shinichi Minami ,  Toru Kaga

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/78 ,  H01L29/7883

摘要： In a semiconductor device which includes an insulation film through which a charge can tunnel, a gate insulation film of a material different from the material of said insulation film or having a thickness different from that of said insulation film, and a floating gate extending over said tunnelable insulation film, the improvement wherein at least two sides of said tunnelable region are bounded by a device separation oxide film.

摘要翻译： 在包括电荷可以隧道穿过的绝缘膜的半导体器件中，与所述绝缘膜的材料不同的或者具有与所述绝缘膜的厚度不同的材料的栅绝缘膜，以及在所述绝缘膜上延伸的浮栅 隧道绝缘膜，其中所述可隧道区域的至少两侧由器件分离氧化物膜限制。

公开(公告)号：US4514830A

公开(公告)日：1985-04-30

申请号：US344974

申请日：1982-02-02

申请人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

发明人： Takaaki Hagiwara ,  Masatada Horiuchi ,  Ryuji Kondo ,  Yuji Yatsuda ,  Shinichi Minami

IPC分类号： H01L27/112 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C29/789

摘要： An LSI memory comprises a memory array including usual memory cells arranged in a matrix form, usual address transistors for selecting usual lines connected to the columns or rows of the memory array, address lines for controlling the usual address transistors, spare memory cells provided in the memory array, a spare line connected to the spare memory cells, spare address transistors connected between the address lines and the spare lines, and nonvolatile memory elements connected between the sources of the spare address transistors and the ground. By putting any one of the nonvolatile memory elements into the written state, any one of the spare address transistors are conditioned into an active state so that the spare line can be substituted for a defective usual line.

摘要翻译： LSI存储器包括存储器阵列，其包括以矩阵形式布置的常规存储器单元，用于选择连接到存储器阵列的列或行的常用线的常用地址晶体管，用于控制通常地址晶体管的地址线，设置在存储器阵列中的备用存储器单元 存储器阵列，连接到备用存储器单元的备用线路，连接在地址线和备用线路之间的备用地址晶体管，以及连接在备用地址晶体管的源极和地之间的非易失性存储器元件。 通过将非易失性存储器元件中的任何一个置于写入状态，任何一个备用地址晶体管被调节成活动状态，使得备用线可以代替缺陷通常的线。

公开(公告)号：US4656607A

公开(公告)日：1987-04-07

申请号：US632317

申请日：1984-07-19

申请人： Takaaki Hagiwara ,  Toru Kaga ,  Hiroo Masuda

发明人： Takaaki Hagiwara ,  Toru Kaga ,  Hiroo Masuda

IPC分类号： H01L27/112 ,  G11C11/40 ,  G11C11/404 ,  G11C14/00 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7881 ,  G11C11/404 ,  G11C16/0408

摘要： In a semiconductor memory made up of semiconductor memory elements, each consisting of a transistor of an MOS structure which has a charge-storage layer and which is formed on a semiconductor substrate, the improvement wherein a switching element is provided so that positive or negative charge can be stored or discharged from the charge-storage layer in a mode for writing data, and the charge-storage layer can be allowed to float electrically when in a mode for reading data.

摘要翻译： 在由半导体存储元件构成的半导体存储器中，每个由具有电荷存储层的MOS结构的晶体管构成，并形成在半导体衬底上，其特征在于，提供一种开关元件，使得正或负电荷 可以以用于写入数据的模式从电荷存储层存储或放电，并且当处于读取数据的模式时，可以允许电荷存储层电浮动。

公开(公告)号：US5340760A

公开(公告)日：1994-08-23

申请号：US992473

申请日：1992-12-15

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： A01H5/02 ,  H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/335

CPC分类号： A01H5/02 ,  H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5079603A

公开(公告)日：1992-01-07

申请号：US517386

申请日：1990-04-30

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886 ,  H01L27/105 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US5472891A

公开(公告)日：1995-12-05

申请号：US260229

申请日：1994-06-14

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukuda ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukuda ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/266 ,  H01L21/8247

CPC分类号： H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并且采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5189497A

公开(公告)日：1993-02-23

申请号：US765065

申请日：1991-09-24

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/105 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US5604142A

公开(公告)日：1997-02-18

申请号：US419232

申请日：1995-04-10

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/8247

CPC分类号： H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。